DRAM 1T Cell

The 1T-1C DRAM cell is the dominant choice for high-density main memory because it uses only one transistor and one capacitor per bit, making it far more area-efficient than SRAM. However, the stored charge on the capacitor leaks over time and the read operation is destructive, requiring careful design of sensing and refresh circuits. These characteristics define all DRAM system behavior and are important topics in both VLSI design courses and GATE examinations.

Core Concept: Structure of the 1T-1C Cell

The DRAM cell consists of a single NMOS access transistor (T1) and a single storage capacitor (Cs). The gate of T1 is connected to the wordline (WL). The drain of T1 connects to the bitline (BL), and the source connects to the top plate of Cs. The bottom plate of Cs is tied to a reference voltage, typically VDD/2 or GND depending on the design. Storing logic 1 means charging Cs to VDD (or VDD/2 relative to reference), and storing logic 0 means leaving Cs discharged.

The key difference from SRAM is that there is no active feedback. The data exists purely as a charge packet on Cs. Leakage currents from the reverse-biased junction of T1 and subthreshold conduction slowly drain this charge. Once the charge falls below a threshold, the stored bit can no longer be reliably read. This is why DRAM requires periodic refresh every few milliseconds to recharge the capacitor back to its correct value.

Mathematical Expression: Charge Sharing Sensing

Before a read, the bitline is precharged to VDD/2 using a precharge circuit. This is called the equilibration phase. When the wordline is asserted, the charge stored on Cs is shared with the bitline capacitance C_BL. The final voltage on the bitline after charge sharing is determined by charge conservation:

Cs x V_cell + C_BL x (VDD/2) = (Cs + C_BL) x V_final

The voltage deviation from the precharge level (VDD/2) is: DeltaV = Cs / (Cs + C_BL) x (V_cell - VDD/2). Since Cs is typically 20 to 30 fF and C_BL is 100 to 200 fF, the ratio Cs/C_BL is about 0.1 to 0.2, giving DeltaV of only 50 to 100 mV even when V_cell is full VDD/2 swing. The sense amplifier must reliably detect and amplify this tiny signal. This is much harder than SRAM sensing because the signal is smaller and the read is destructive.

Practical Understanding: Destructive Read and Restore

Because charge sharing redistributes the charge across both Cs and C_BL, the voltage on Cs is no longer its original stored value after a read. This means the read operation destroys the stored data. After the sense amplifier amplifies the differential to full logic swing, it drives the bitline to VDD or GND. This voltage is then written back into the cell through the still-open access transistor. This automatic restore operation is part of every DRAM read cycle and is handled by the sense amplifier itself.

The DRAM cell capacitor Cs is not a simple planar capacitor. In modern DRAM, Cs is implemented as a trench capacitor (digging deep into the silicon substrate) or a stacked capacitor (building vertically above the transistor). These structures allow Cs of 20 to 30 fF to be maintained even as cell dimensions shrink to sub-20 nm. Maintaining Cs is critical because reducing it below about 10 to 15 fF makes sensing unreliable and increases refresh frequency.

The access transistor T1 must have very low off-state leakage to maintain charge on Cs for the required retention time (typically 64 ms). High-k gate dielectric and channel doping optimization are used to reduce subthreshold leakage while maintaining reasonable on-state drive current for fast access. This is a fundamental trade-off in DRAM technology scaling.

Given:
Storage capacitor Cs = 25 fF
Bitline capacitance C_BL = 150 fF
Precharge voltage V_pre = VDD/2 = 0.5 V
VDD = 1.0 V
Stored bit = 1, so V_cell = VDD = 1.0 V

Why this formula applies:
Charge sharing between Cs and C_BL determines the read signal.
Conservation of charge gives final bitline voltage.

Formula:
DeltaV = Cs / (Cs + C_BL) x (V_cell - V_pre)

Substitution:
DeltaV = 25 / (25 + 150) x (1.0 - 0.5)
= 25 / 175 x 0.5

Calculation:
= 0.1429 x 0.5
= 0.0714 V = 71.4 mV

For stored bit = 0, V_cell = 0 V:
DeltaV = 25 / 175 x (0 - 0.5) = -71.4 mV (bitline drops)

Differential signal between BL and reference = 71.4 mV.
Sense amplifier must resolve this with < 5% error probability.

Final Answer: Bitline voltage deviation = 71.4 mV for stored 1 and -71.4 mV for stored 0.

Exam Tip: GATE frequently asks about the DRAM read signal. Remember DeltaV = Cs/(Cs + C_BL) x VDD/2. The signal is small because C_BL >> Cs. Also note: read is destructive in DRAM but not in SRAM. The sense amplifier restores the cell in DRAM automatically.

Charge Leakage and Retention

• Capacitor Cs stores charge. Leakage currents from T1 (subthreshold, junction, GIDL) continuously drain this charge.
• When Vcell drops below the sensing threshold, the bit can no longer be reliably read. Refresh must happen before this.
• Retention time is determined by the worst cell (highest leakage cell) in the entire DRAM array, not the average.
• Refresh period is standardized at 64 ms at room temperature. At elevated temperatures (85 degrees C), retention time halves, requiring faster refresh.
• Read is destructive: charge sharing reduces Vcell after every read. The sense amplifier restores the cell automatically.

Quick Revision

• DRAM cell = 1 NMOS transistor + 1 capacitor. Logic 1 = charged capacitor, Logic 0 = discharged capacitor.
• Read signal: DeltaV = Cs / (Cs + C_BL) x VDD/2. Typically 50 to 100 mV due to C_BL >> Cs.
• Read is destructive. Sense amplifier must restore cell data after every read.
• Charge leaks due to transistor leakage. Refresh is needed every 64 ms to restore stored charge.
• Capacitor built as trench or stacked structure to maintain 20 to 30 fF even at sub-20 nm technology nodes.
• GATE trap: DRAM has higher density than SRAM (1T+1C vs 6T) but is slower and requires refresh. SRAM is faster but much larger per bit.
• Worst-case cell (highest leakage) determines the refresh rate for the entire array.