SRAM 6T Cell

The 6T SRAM cell is the fundamental building block of all static RAM memories used in caches, register files, and embedded memory in modern processors. Unlike DRAM, an SRAM cell holds its stored value as long as power is supplied, requiring no periodic refresh. Understanding its read and write operation is central to VLSI design and is a high-frequency topic in GATE and placement interviews.

Core Concept: 6T SRAM Cell Structure

The 6T SRAM cell consists of two cross-coupled CMOS inverters and two access transistors (pass gates). The two inverters form a bistable latch. Each inverter consists of one PMOS pull-up transistor and one NMOS pull-down transistor. The output of each inverter drives the input of the other, creating two stable states: Q=1, QB=0 or Q=0, QB=1. The cell holds this state indefinitely as long as supply voltage is maintained.

The two access transistors, labeled PG1 and PG2 (pass gate or access gate), connect the internal nodes Q and QB to the bit lines BL and BLB respectively. These transistors are controlled by the wordline (WL). When WL is low, the access transistors are off and the cell is isolated from the bit lines, maintaining its stored value (hold mode). When WL is asserted high, both access transistors turn on and the cell either delivers data to the bit lines (read) or accepts new data from the bit lines (write).

Mathematical Expression: Cell Ratio and Stability

Two transistor sizing ratios govern the functionality of the 6T SRAM cell. The cell ratio (CR) is defined as the ratio of the drive strength of the pull-down transistor (PD) to the drive strength of the access transistor (PG): CR = (W/L)_PD / (W/L)_PG. A higher CR ensures that during a read operation, the internal node voltage does not rise high enough to flip the stored bit. A minimum CR of 1.5 to 2 is typically required for stable read operation.

The pull-up ratio (PR) is defined as PR = (W/L)_PG / (W/L)_PU. During a write operation, the access transistor must overpower the pull-up PMOS transistor to flip the cell. A PR greater than 1 (meaning PG is stronger than PU) is needed for reliable write. These two conditions conflict: read stability demands strong PD relative to PG, while write ability demands strong PG relative to PU. This tension is the central design challenge of SRAM cells.

Practical Understanding: Read and Write Operations

During a read operation, both BL and BLB are precharged to VDD. The wordline is then asserted. Suppose Q stores logic 1 (QB = 0). BLB connects to QB (which is at GND) through PG2. Current flows from BLB through PG2 and PD2 to ground, causing BLB to discharge slightly. BL stays near VDD because PG1 connects to Q which is at VDD and PU1 holds it up. The sense amplifier detects this small differential voltage between BL and BLB and amplifies it to a full logic level. The read failure occurs if the voltage at QB (the 0-storing node) rises above the switching threshold of the inverter, causing the cell to flip. A sufficient cell ratio prevents this.

During a write operation, the write driver forces BL to the desired value and BLB to its complement. For example, to write 0 to Q, BL is pulled to GND and BLB is driven to VDD. When WL is asserted, BL pulls node Q toward GND through PG1. The pull-up PU1 fights this, but if PG1 is sized appropriately (PR > 1), Q is pulled below the switching threshold of the second inverter, causing both inverters to flip to the new state. Write failure occurs if the pull-up PMOS is too strong relative to the access transistor.

Given:
PD transistor (W/L) = 4 (pull-down, NMOS)
PG transistor (W/L) = 2 (access, NMOS)
PU transistor (W/L) = 1 (pull-up, PMOS)

Why this formula applies:
Cell ratio determines read stability. Pull-up ratio determines write ability.

Formula:
CR = (W/L)_PD / (W/L)_PG
PR = (W/L)_PG / (W/L)_PU

Substitution:
CR = 4 / 2 = 2
PR = 2 / 1 = 2

Calculation:
CR = 2 (>= 1.5, so read is stable)
PR = 2 (> 1, so write can overcome pull-up)

Read noise margin check:
Voltage at 0-node during read rises to approximately:
VQ_rise = VDD x (W/L)_PG / ((W/L)_PD + (W/L)_PG)
= 1.0 x 2 / (4 + 2) = 0.333 V
If switching threshold of inverter > 0.333 V, cell is read-stable.

Final Answer: CR = 2 (stable read), PR = 2 (successful write). Both conditions satisfied.

Exam Tip: In GATE, if asked which transistor must be widest in a 6T SRAM, the answer is PD (pull-down NMOS). CR must exceed 1.5, so PD must be the strongest transistor. Also remember: PU is always the weakest (narrowest) to enable writes.

Quick Revision

• 6T SRAM = 2 cross-coupled inverters (4 transistors) + 2 access transistors (PG1, PG2) controlled by wordline.
• Hold mode: WL = 0. Cell isolated. State maintained by positive feedback of cross-coupled inverters.
• Read: BL and BLB precharged. WL asserted. Differential discharge sensed by sense amplifier.
• Write: BL driven to new value. WL asserted. Access transistor must overcome pull-up to flip cell.
• Cell ratio CR = (W/L)_PD / (W/L)_PG. Must be >= 1.5 for read stability. Higher CR = more stable reads.
• Pull-up ratio PR = (W/L)_PG / (W/L)_PU. Must be > 1 for successful write.
• GATE trap: Read and write constraints on transistor sizing conflict. PD must be widest, PU must be narrowest.