Flash Memory Cell

Flash memory is the dominant non-volatile storage technology in modern electronics, found in USB drives, SSDs, smartphones, and embedded systems. Unlike ROM, flash can be electrically erased and reprogrammed. The key to this capability is the floating gate transistor, a specially constructed MOSFET with an electrically isolated polysilicon gate that can trap charge indefinitely. Understanding the floating gate mechanism is fundamental to VLSI memory design and is regularly examined in GATE.

Core Concept Explanation

A floating gate transistor differs from a standard MOSFET by having two polysilicon gate layers instead of one. The bottom gate, called the floating gate (FG), is completely surrounded by high-quality silicon dioxide and has no electrical connection to any terminal. The top gate is the control gate (CG), which is the terminal that the external circuit drives. Between the floating gate and the substrate lies a very thin oxide layer called the tunnel oxide, typically 7 to 10 nm thick.

When electrons are injected into the floating gate, they become trapped there indefinitely because they are surrounded by insulating oxide on all sides. This stored charge shifts the threshold voltage of the transistor. Specifically, a negative charge (electrons) on the floating gate creates a field that opposes the positive field needed to form an inversion layer in the substrate, so more gate voltage is required to turn the transistor on. The threshold voltage increases with stored electrons. This programmed state is read as logic 0.

When no charge is present on the floating gate, the transistor has its natural threshold voltage, which is relatively low. A read voltage applied between the two states can distinguish whether the transistor turns on (erased, logic 1) or stays off (programmed, logic 0). This is the fundamental read mechanism for a flash cell. The charge can remain on the floating gate for 10 years or more under normal conditions, which is the basis for non-volatile storage.

Mathematical Expression

The threshold voltage of the floating gate cell is given by a modified expression that accounts for the stored charge. If Q_FG is the charge stored on the floating gate (in Coulombs, negative for electrons) and C_ONO is the capacitance of the inter-poly dielectric layer (oxide-nitride-oxide stack between CG and FG), then the effective threshold voltage seen from the control gate is:

V_th_eff = V_th0 - Q_FG / C_ONO

Here V_th0 is the intrinsic threshold voltage with no stored charge. When Q_FG is negative (electrons stored), the term -Q_FG / C_ONO is positive, raising V_th_eff. The coupling ratio alpha = C_ONO / (C_ONO + C_tunnel) determines how effectively the control gate voltage modulates the floating gate potential. A coupling ratio close to 1 means the control gate has strong influence, which is desired for programming efficiency.

Practical Understanding

Programming (writing a 0) is done by applying a high positive voltage to the control gate (typically 15 to 20 V for older technologies, lower for scaled nodes) while grounding the source. This creates a high electric field across the thin tunnel oxide, enabling electrons to tunnel from the channel into the floating gate via Fowler-Nordheim (FN) tunneling. In some cells, hot carrier injection (HCI) is used instead, where high-energy channel electrons are injected into the floating gate by a lateral drain field.

Erasing (restoring a 1) is done by applying a high positive voltage to the source (or substrate) while the control gate is held at zero or negative voltage. This reverses the field across the tunnel oxide and pulls electrons back out of the floating gate into the channel, reducing V_th back to its natural value.

Repeated program-erase cycles cause wear to the tunnel oxide, a phenomenon called oxide degradation. Typical flash cells tolerate 10,000 to 100,000 cycles (for NOR flash) or 3,000 to 10,000 cycles (for NAND flash). Beyond this, charge trapping in the tunnel oxide causes permanent threshold voltage shift, leading to read errors. This endurance limitation is a fundamental constraint in flash memory design.

Given:
Intrinsic threshold voltage V_th0 = 0.7 V
Stored charge on floating gate Q_FG = -2e-15 C (electrons)
Capacitance of ONO dielectric C_ONO = 5e-15 F

Why this formula applies:
Stored electrons shift the effective threshold voltage seen at the control gate.
V_th_eff = V_th0 - Q_FG / C_ONO

Formula:
V_th_eff = V_th0 - Q_FG / C_ONO

Substitution:
V_th_eff = 0.7 - (-2e-15) / (5e-15)

Calculation:
V_th_eff = 0.7 - (-0.4)
V_th_eff = 0.7 + 0.4

Final Answer:
V_th_eff = 1.1 V (threshold raised by 0.4 V due to stored electrons)

Exam Tip: GATE often asks whether programming increases or decreases threshold voltage. For NMOS floating gate cells, programming stores electrons which always INCREASES V_th. Erasing removes electrons and DECREASES V_th. Confusing this direction is the most common mistake in flash memory questions.

• Floating gate stores electrons permanently due to full oxide isolation. No power is needed to retain charge, making storage non-volatile.
• Programming applies high V_CG. Fowler-Nordheim tunneling drives electrons from channel into floating gate through tunnel oxide. V_th increases.
• Erasing applies high V_source or V_substrate. Reverse field pulls electrons out of floating gate. V_th returns to natural low value.
• Read applies a voltage V_read set between erased V_th and programmed V_th. If cell conducts, bit is 1. If cell does not conduct, bit is 0.
• MLC (Multi-Level Cell) flash stores 2 bits per cell by using 4 distinct threshold voltage levels instead of 2, doubling density at the cost of reduced margin and endurance.

Quick Revision

• Flash cell = standard MOSFET + floating gate sandwiched between tunnel oxide (below) and IPD (above) + control gate on top.
• Program: high V_CG, electrons tunnel in, V_th increases, cell stores 0.
• Erase: high V_source, electrons tunnel out, V_th decreases, cell stores 1.
• Threshold shift formula: V_th_eff = V_th0 - Q_FG / C_ONO. Negative Q_FG (electrons) raises V_th.
• Coupling ratio alpha = C_ONO / (C_ONO + C_tunnel) should be close to 1 for efficient programming.
• GATE trap: programming INCREASES V_th for NMOS floating gate cell. Do not confuse with PMOS convention.
• Endurance limit: ~100K cycles for NOR flash, ~10K for NAND flash, due to tunnel oxide wear.