Layout Basics

Physical layout is the final representation of a VLSI circuit that is sent for fabrication. It consists of stacked geometric patterns on different process layers, each corresponding to a material or doping step in the semiconductor manufacturing process. Understanding how these layers are defined, what they represent physically, and how they interact is essential for anyone working in VLSI design, and this topic carries consistent weight in both university examinations and GATE.

Core Concept: Process Layers in CMOS Layout

A CMOS layout consists of multiple patterned layers, each defined by a lithographic mask. The active layer (also called diffusion) defines the regions of the silicon substrate where transistors can be formed. N-type active regions form NMOS source-drain junctions, while P-type active regions form PMOS junctions. The N-well layer defines which portions of the substrate are converted to N-type for PMOS fabrication.

The polysilicon layer serves as the gate electrode of all transistors. Wherever polysilicon overlaps an active region, a transistor gate is formed. The thin gate oxide underneath the poly, typically 2-5 nm in advanced nodes, separates the gate from the channel. Polysilicon also functions as a local interconnect within a standard cell, though it has higher sheet resistance than metal.

Metal layers provide the global and semi-global interconnects. Metal-1 typically runs horizontally within a standard cell for power routing (VDD, GND rails) and local signal connections. Metal-2 runs vertically for routing between cells. As process nodes shrink, the number of metal layers increases (up to 12 or more in advanced nodes) because the routing demand grows faster than the transistor density alone can handle.

Mathematical Expression: Sheet Resistance and RC Delay

Every conductive layer in a layout has a sheet resistance R_sq (measured in ohms per square). This is a fundamental concept for estimating wire delay. The resistance of a rectangular wire segment is R = R_sq x (L / W), where L is the length and W is the width of the wire. For polysilicon, R_sq is typically 20-50 ohm/sq, whereas for metal it is 0.05-0.1 ohm/sq. This is why poly is never used for long-distance interconnect.

Contacts and vias also add resistance. A single contact plug has a contact resistance of about 20-50 ohms. When routing high-current nodes like VDD and GND, designers place multiple contacts in parallel to reduce total resistance. The number of contacts required is estimated from the maximum current and acceptable voltage drop across the connection.

Practical Understanding: Design Rules for Each Layer

Design rules exist for every layer and every interaction between layers. The most commonly tested rules are the minimum width of a layer (preventing open circuits due to etch undercut), the minimum spacing between two features on the same layer (preventing shorts), and the minimum overlap or enclosure rules (ensuring contacts remain inside the layer they connect to).

For example, a contact cut must be fully enclosed by the metal layer above and the poly or diffusion layer below. If the contact is placed too close to the edge of the active region, the enclosure rule is violated. Similarly, two metal wires on the same layer must maintain a minimum spacing (typically 3λ or a specified nm value in modern rule decks) to prevent capacitive coupling and lithographic merging.

Numerical Example

Given:
Polysilicon sheet resistance R_sq = 30 Ω/sq
Poly wire length L = 10 μm
Poly wire width W = 0.5 μm
Gate oxide capacitance C_ox = 8 fF/μm²
Gate area = L_gate × W_gate = 0.18 μm × 1 μm

Why this formula applies:
Sheet resistance model gives wire resistance. Gate capacitance is area-based.

Formula:
R_wire = R_sq × (L / W)
C_gate = C_ox × (L_gate × W_gate)

Substitution:
R_wire = 30 × (10 / 0.5) = 30 × 20
C_gate = 8 fF/μm² × (0.18 × 1) μm²

Calculation:
R_wire = 600 Ω
C_gate = 8 × 0.18 = 1.44 fF
RC delay contribution = R_wire × C_gate = 600 × 1.44×10⁻¹⁵
= 864 × 10⁻¹⁵ s = 0.864 ps

Final Answer:
Poly wire resistance = 600 Ω
Gate capacitance = 1.44 fF
RC delay = 0.864 ps (significant at GHz speeds)

Exam Tip: Questions on layout often show a partial cross-section and ask which layer is which. Remember: the gate electrode is always polysilicon, not metal. Contacts go from poly/diffusion to Metal-1. Vias go from Metal-N to Metal-(N+1). Confusing contacts with vias is a frequent error in GATE answers.

Mechanism: Contacts and Vias in Layout

• The active layer defines transistor source-drain regions. Its boundaries must not be violated by contacts or any other layer that would cause unintended junctions.
• Polysilicon over active = transistor. Polysilicon over field oxide = resistor or local wire, but with much higher resistance and no transistor action.
• Contact cuts connect the poly or diffusion layer to Metal-1. They are distinct from vias, which connect Metal-1 to Metal-2 or higher. In a DRC file, these are separate layer objects.
• Enclosure rules mandate that a contact or via must be surrounded by the connecting layer by at least a specified distance on all sides. Failing this causes an open circuit during fabrication.
• Sheet resistance of poly (20-50 ohm/sq) is far higher than Metal-1 (0.05-0.1 ohm/sq). Poly should never be used as a long-distance interconnect. This is a foundational layout optimization principle.

Quick Revision

• Layers: Active (diffusion), Polysilicon, N-well, Contact, Metal-1, Via-1, Metal-2. Each has specific width, spacing, and enclosure rules.
• Transistor = poly crossing active. No poly over active = no transistor, even if diffusion is present.
• Contact connects poly/diffusion to M1. Via connects M1 to M2. Confusing these is a common exam mistake.
• Formula: R = R_sq × (L/W). Poly R_sq is ~100x higher than metal. Always use metal for long wires.
• Enclosure rule: contact must be ≥ 1λ inside the surrounding layer on all sides. Violation = open circuit.
• Multiple contacts in parallel reduce resistance for high-current connections such as power rails.
• Exam trap: VDD and GND rails use Metal-1 inside cells but Metal-2 or higher for global routing. Asking which layer routes power depends on the scope (local cell vs chip-level).