SRAM Array Org

A single SRAM cell stores only one bit. A practical memory module requires millions of such cells organized into a structured array. The SRAM array organization defines how cells are connected, accessed, and read or written using row decoders, column multiplexers, sense amplifiers, and write drivers. Understanding this organization is essential for cache design, VLSI physical design, and is directly examined in GATE.

Core Concept: Array Organization Hierarchy

A memory array of N total bits arranged as R rows and C columns requires a row decoder to select exactly one wordline from R wordlines, and a column multiplexer to select a subset of the C bitline pairs for reading or writing. The address input is split: the upper bits select the row, and the lower bits select the column. Each row contains C cells, and when a wordline is asserted, all C cells in that row connect their internal nodes to the respective bitline pairs simultaneously.

The column multiplexer reduces the number of sense amplifiers needed. If the column mux ratio is M, then only C/M sense amplifiers are required instead of C. For example, a 256-column array with a 4:1 column mux needs only 64 sense amplifiers. Each sense amplifier is a differential amplifier that detects the small voltage difference that develops on the BL and BLB pair after wordline assertion, amplifying it to full logic swing in a few hundred picoseconds.

Mathematical Expression: Array Dimensioning

For a memory of total capacity B bits, if it is organized as R rows and C columns, then R x C = B. The row decoder requires log2(R) address inputs, and the column decoder requires log2(C) address inputs. The total address bus width is log2(B) = log2(R) + log2(C). The square array principle states that setting R = C = sqrt(B) minimizes the sum of wordline and bitline lengths, which minimizes RC delay and area. For a 16 Kb array, a 128 x 128 organization is optimal. In practice, arrays are divided into sub-arrays or banks to keep bitline length short, as longer bitlines have higher capacitance and degrade read speed.

The precharge circuit drives BL and BLB to VDD (or VDD/2 in some designs) before every read cycle. The equalizer transistor connects BL and BLB together momentarily to ensure they start at exactly the same voltage, maximizing the symmetry of the differential sensing. Even a few millivolts of initial imbalance can cause sense amplifier errors.

Practical Understanding

In large arrays, the bitline capacitance is the dominant limitation. Each bitline connects to all cells in its column, accumulating the drain capacitance of hundreds of access transistors. During a read, only one cell (the selected one) drives the bitline. The cell must develop a differential voltage of at least 50 to 100 mV on the bitline for the sense amplifier to operate reliably. This differential develops as DeltaV = (C_cell / C_BL) x VDD, where C_cell is the storage node capacitance and C_BL is the total bitline capacitance. A longer bitline means a smaller DeltaV, requiring a more sensitive and slower sense amplifier.

This is why modern SRAMs are divided into multiple sub-arrays. Each sub-array has shorter bitlines, smaller capacitance, faster sensing, and lower power. A global row decoder activates the appropriate sub-array, and a local row decoder within the sub-array asserts the correct wordline. Similarly, hierarchical bitlines use local bitlines within sub-arrays connected to global bitlines through isolation transistors, further reducing capacitance and enabling faster reads.

Given:
Memory array: 1 Kbit (1024 bits)
Organization: 32 rows x 32 columns
Column mux ratio M = 4
Bitline capacitance per cell: C_cell_contribution = 5 fF
Storage node capacitance: C_storage = 10 fF
VDD = 1.0 V

Why this formula applies:
Read margin depends on the voltage swing developed on the bitline.
Smaller bitline capacitance relative to storage node gives larger swing.

Formula:
C_BL = N_rows x C_cell_contribution = 32 x 5 fF
DeltaV = (C_storage / C_BL) x VDD

Substitution:
C_BL = 32 x 5 fF = 160 fF
DeltaV = (10 fF / 160 fF) x 1.0 V

Calculation:
DeltaV = 0.0625 V = 62.5 mV

Number of sense amplifiers needed:
With 32 columns and mux ratio 4: SA count = 32 / 4 = 8 sense amplifiers per data bit width.

Final Answer: Bitline swing = 62.5 mV. Number of sense amplifiers = 8 for 32-column array with 4:1 mux.

Exam Tip: For GATE memory organization questions, remember that doubling the number of rows in an array halves the bitline swing, directly degrading read speed. The square array (R = C = sqrt(total bits)) minimizes total wire length and is the standard optimization. Always split address bits as upper = row, lower = column.

SRAM Array Peripheral Circuits

• Address is split into row bits and column bits. Row bits drive the row decoder, column bits drive the column mux select lines.
• Precharge phase: BL and BLB are pulled to VDD and equalized. This sets a clean starting condition before the read.
• WL assertion: Row decoder drives the selected wordline high, connecting all cells in that row to their respective bitlines simultaneously.
• Bitline discharge: The selected cell develops a differential voltage on BL/BLB. Only one side discharges depending on stored bit.
• Column mux selects the correct BL/BLB pair based on column address and routes it to the sense amplifier input.
• Sense amplifier fires and amplifies the small differential (as low as 50 mV) to full logic swing in a few hundred picoseconds.

Quick Revision

• SRAM array: R rows x C columns. Row decoder selects WL. Column mux selects BL pair. Sense amplifier reads differential.
• Square array rule: R = C = sqrt(total bits) minimizes wordline and bitline lengths, optimizing speed and area.
• Bitline swing: DeltaV = (C_storage / C_BL) x VDD. Longer bitline = smaller swing = slower sensing.
• Sub-array division reduces bitline capacitance and improves read speed. Used in all modern large SRAMs.
• Column mux ratio M reduces sense amplifier count from C to C/M. Trade-off: slower column access with higher M.
• GATE trap: Precharge is essential before every read cycle. Forgetting to model BL capacitance leads to underestimating access time.