SR Latch

The SR latch is the most fundamental sequential storage element in digital design. It directly implements the bistable principle using two cross-coupled logic gates and provides separate Set and Reset inputs to steer the circuit to a desired stable state. Understanding the SR latch at both the logic level and the transistor level is foundational for analyzing all complex flip-flop and memory structures.

NOR-Based SR Latch

The NOR-based SR latch uses two cross-coupled NOR gates. The S (Set) input drives one NOR gate, and the R (Reset) input drives the other. When S=1 and R=0, the output Q is forced to 1 because the NOR gate with S=1 at its input produces 0 at its output (which becomes Qb), and the other NOR gate with both inputs 0 produces Q=1. This Q=1 state is then maintained by the cross-coupling even after S returns to 0.

When both S and R are 0, the latch retains its previous state. This is the memory or hold condition: neither gate is being forced, so the circuit stays at whichever of the two stable states it was last driven to. This is the fundamental storage mechanism that all sequential logic relies on.

The forbidden condition is S=R=1. With both inputs high, both NOR gates produce a 0 output, forcing Q=Qb=0, which violates the complementary relationship between Q and Qb. More critically, when S and R simultaneously return to 0 from this condition, the latch enters a race condition and the final state is unpredictable — it depends on which gate switches faster, which is process- and noise-dependent.

NAND-Based SR Latch

The NAND-based SR latch uses two cross-coupled NAND gates and operates with active-low inputs, conventionally written as Sb (Set-bar) and Rb (Reset-bar). When Sb=0 and Rb=1, the NAND gate with Sb=0 forces its output to 1 regardless of the feedback, which becomes Q=1. This is the Set condition. Similarly, Rb=0 resets the latch to Q=0.

The hold condition is Sb=Rb=1, and the forbidden condition is Sb=Rb=0 (both inputs low). In the forbidden state, both NAND gates produce 1 at their outputs, so Q=Qb=1, which again violates the complement relationship. The NAND latch is preferred in many implementations because NAND gates are inherently faster than NOR gates in CMOS technology due to the series PMOS structure of NOR being slower than the series NMOS structure of NAND.

Mathematical Expression

The characteristic equation of the SR latch defines the next state Q+ as a function of current inputs S, R, and current state Q:

Q+ = S + (R' x Q) with the constraint S x R = 0 (forbidden condition). This equation captures all three operating modes: if S=1, Q+ = 1 (set); if R=1, Q+ = 0 (reset); if S=R=0, Q+ = Q (hold). The constraint S x R = 0 must be enforced externally to guarantee valid operation.

Practical Understanding

SR latches appear directly in standard cell libraries as fundamental sequential primitives. They are used in clock gating cells, set/reset flip-flops, and as the internal storage core of D latches and D flip-flops. In a D latch, the D input and its complement are steered to the S and R inputs of an SR latch under clock control. When the clock is high, D is passed through to S and Db to R; when the clock goes low, S=R=0 and the latch holds its last state.

In CMOS implementation, a NOR-based SR latch requires 4 PMOS and 4 NMOS transistors (2 NOR gates), while a NAND-based SR latch also requires 4 PMOS and 4 NMOS transistors. However, since the series PMOS stack in a NOR gate has higher resistance than the series NMOS stack in a NAND gate, the NAND latch has lower propagation delay and is more commonly chosen in high-speed design.

The setup time and hold time of SR latches refer to how long the S or R input must be stable before and after the trigger event for reliable state capture. Violating these constraints pushes the latch toward the metastable region, with resolution governed by the loop gain of the cross-coupled gates.

Given:
NOR-based SR latch with CMOS NOR gates
VDD = 1.2V, each NOR gate: t_pHL = 80 ps, t_pLH = 120 ps
Cross-coupled feedback capacitance C_fb = 8 fF
gm per gate = 1.5 mA/V

Why this formula applies:
The propagation delay of the latch set operation depends on the NOR gate delay plus the feedback settling time.

Formula:
t_set = t_pHL_NOR1 + t_pLH_NOR2 (series path through two gates)
tau_feedback = C_fb / gm

Substitution:
t_set = 80 ps + 120 ps = 200 ps (first-order estimate)
tau_feedback = 8e-15 / 1.5e-3

Calculation:
tau_feedback = 5.33 ps

The feedback settles approximately 3 to 5 tau after the initial transition:
t_settle = 5 x 5.33 = 26.7 ps (additional settling)

Total latch set time = 200 + 26.7 = ~227 ps

Final Answer:
Approximate SR latch set operation time = 227 ps.
The feedback loop settles in approximately 27 ps, which is much smaller than the gate delay, confirming the latch is in a valid stable state within one gate delay cycle.

Exam Tip: GATE frequently tests the forbidden condition: for NOR SR latch it is S=R=1 (Q=Qb=0), for NAND SR latch it is Sb=Rb=0 (Q=Qb=1). Remember NOR = active-high inputs, NAND = active-low inputs. This distinction is a very common exam question.

CMOS Implementation and Race Condition

• NOR SR latch: active-high inputs; Set (S=1) forces Q=1, Reset (R=1) forces Q=0, hold at S=R=0, forbidden at S=R=1.
• NAND SR latch: active-low inputs Sb/Rb; Set (Sb=0) forces Q=1, Reset (Rb=0) forces Q=0, hold at Sb=Rb=1, forbidden at Sb=Rb=0.
• Forbidden state causes Q=Qb (either both 0 in NOR or both 1 in NAND), violating the complementary output requirement.
• Race condition occurs when the forbidden state is released simultaneously; final state depends on whichever gate's input falls first.
• NAND latch is faster in CMOS because NAND pull-down uses series NMOS (lower resistance) while NOR pull-up uses series PMOS (higher resistance).
• Characteristic equation: Q+ = S + R' x Q with constraint SR=0. This summarizes all valid state transitions in one expression.

Quick Revision

• NOR SR latch: active-high (S=1 sets, R=1 resets, S=R=0 holds, S=R=1 forbidden Q=Qb=0).
• NAND SR latch: active-low (Sb=0 sets, Rb=0 resets, Sb=Rb=1 holds, Sb=Rb=0 forbidden Q=Qb=1).
• Characteristic equation: Q+ = S + R'Q, constraint: SR = 0.
• NAND latch preferred in CMOS for speed: NAND pull-down is faster than NOR pull-up due to NMOS vs PMOS series stacks.
• Race condition: simultaneous removal of S=R=1 causes unpredictable final state due to gate delay mismatch.
• GATE trap: the forbidden input for NOR latch is S=R=1 (both high), not S=R=0. Students often confuse this with the NAND latch forbidden condition (Sb=Rb=0, both low).
• SR latch is the fundamental storage cell inside D latches and D flip-flops; the D input steers S and Rb via a transmission gate under clock control.