SR Latch

The SR latch is the most primitive memory element in digital logic — two cross-coupled NOR or NAND gates that hold a single bit indefinitely. Every static RAM cell, every flip-flop, and every register in a CPU traces its memory behavior back to this circuit.

Core Concept

The SR latch (Set-Reset latch) has two inputs S and R and two complementary outputs Q and Q'. When S=1 R=0, the latch sets (Q=1). When R=1 S=0, it resets (Q=0). When both inputs are 0, the latch holds its last state — this is the memory property. The forbidden condition S=R=1 drives both outputs to 0, violating the Q-Q' complement relationship.

A NOR-based SR latch uses two 74HC02 gates. Propagation delay is 3.5 ns typical at 5 V supply. The active-HIGH inputs mean logic 1 triggers the function. In contrast, a NAND-based SR latch (also called S'R' latch or active-LOW SR latch) uses 74HC00 NAND gates; its forbidden state is S=R=0 instead.

The cross-coupled feedback is what creates bistability. Once set or reset, the output state is self-reinforcing through the feedback path. Removing power clears the state. This makes the SR latch volatile — it cannot retain data without a power supply, unlike flash memory or EEPROM.

Boolean Expression

The characteristic equation (next state) for an SR latch is: Q(next) = S + R' Q with the constraint S·R = 0 (forbidden). For the NAND latch (active-LOW): Q(next) = S' + R·Q' with constraint S'·R' = 0. The NOR latch output for each gate is: upper NOR output = NOR(S, Q') = Q; lower NOR output = NOR(R, Q) = Q'.

Given:
  NOR SR latch, initial state Q=0, Q'=1
  Input sequence: S=1,R=0 → S=0,R=0 → S=0,R=1 → S=0,R=0

Formula / Rule:
  Q(next) = S + R'·Q, constraint S·R = 0

Step by step:
  Step 1: S=1, R=0 → Set
    Q(next) = 1 + 1·0 = 1  → Q=1, Q'=0

  Step 2: S=0, R=0 → Hold
    Q(next) = 0 + 1·1 = 1  → Q=1, Q'=0  (holds previous)

  Step 3: S=0, R=1 → Reset
    Q(next) = 0 + 0·1 = 0  → Q=0, Q'=1

  Step 4: S=0, R=0 → Hold
    Q(next) = 0 + 1·0 = 0  → Q=0, Q'=1  (holds reset state)

Final Answer:
  State sequence Q: 0 → 1 → 1 → 0 → 0
  Latch correctly sets, holds, resets, and holds.

Exam Tip: GATE and university exams often swap NOR and NAND latches to catch students. In a NOR latch, S=R=1 is forbidden. In a NAND latch, S=R=0 is forbidden (active-LOW inputs). Always identify the gate type first. A second trap: the hold state Q(next) = Q is NOT the same as 'both outputs are 0' — hold means the previous Q value is retained, not that both go to zero.

Key Properties

• NOR SR latch: active-HIGH inputs; S=R=1 is forbidden; built from 74HC02.
• NAND SR latch: active-LOW inputs; S=R=0 is forbidden; built from 74HC00.
• 74HC02 propagation delay: 3.5 ns typical at 5 V; fan-out: 50 CMOS loads.
• Characteristic equation: Q(next) = S + R' Q with constraint SR = 0.
• Bistable: two stable states (Q=0 and Q=1); holds state without clock.
• No clock input — asynchronous; responds immediately to input changes.
• Volatile: loses state on power loss; cannot replace non-volatile memory.

Quick Revision

• SR latch: S=Set (Q→1), R=Reset (Q→0), S=R=0 hold, S=R=1 forbidden (NOR type).
• NAND latch: S'=R'=0 forbidden; both active-LOW; complement behavior.
• Characteristic equation: Q(next) = S + R'Q; constraint SR=0.
• No clock — purely asynchronous, immediate response.
• 74HC02 (NOR) and 74HC00 (NAND) are the standard ICs for SR latch construction.
• Cross-coupled feedback gives bistability — self-reinforcing stable states.
• Exam trap: confusing NOR forbidden state (S=R=1) with NAND forbidden state (S=R=0) — they are opposite.