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Contents

Digital Electronics

Number Systems

Binary Number System Octal Number System Hexadecimal Number System Number System Conversions Binary Addition Binary Subtraction 1s Complement 2s Complement Signed Number Representation BCD Code Gray Code Excess-3 Code ASCII Code Error Detection Codes Hamming Code

Logic Gates

AND Gate OR Gate NOT Gate NAND Gate NOR Gate XOR Gate XNOR Gate Universal Gates NAND Universal Gates NOR Multi-Input Gates Buffer Gate TTL Logic Family CMOS Logic Family TTL vs CMOS Comparison Logic Level Interfacing

Boolean Algebra

Boolean Algebra Axioms Boolean Algebra Theorems De Morgan Theorem 1 De Morgan Theorem 2 De Morgan Applications Boolean Expression Simplification Canonical SOP Form Canonical POS Form Minterm and Maxterm Relationship K-Map 2 Variable K-Map 3 Variable K-Map 4 Variable K-Map Don't Care Conditions K-Map POS Simplification Quine-McCluskey Method Prime Implicant Chart

Combinational Circuits

Sequential Circuits

Memory & PLDs

ROM Architecture PROM EPROM and EEPROM SRAM DRAM SRAM vs DRAM Flash Memory PLA PAL CPLD FPGA Architecture FPGA vs ASIC

Digital System Design

Propagation Delay Setup and Hold Time Static Hazards Dynamic Hazards Glitches and Races Synchronous Design Principles Clock Skew and Jitter Asynchronous Circuit Design

Other Topics

Other Subjects

Analog Electronics Signals & Systems Control Systems Electromagnetic Theory Digital Communication Analog Communication Network Analysis Microprocessors VLSI Design Verilog HDL Power Electronics Embedded Systems DSP Electronic Devices

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1 of 27 articles

SR Latch

NOR gate latch, NAND gate latch, invalid state.

Updated: 19 March 2026

7 min read

SR Latch Quiz

Analyze latch behavior and invalid states.

Question 1 of 3

Q1.In a NOR gate SR latch, what is the output state when S=1 and R=1?

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SR Latch

NOR and NAND based latches.

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Edge triggered SR, characteristic equation, excitation table.

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Modeling Latches

Level sensitive behavior, inferring latches accident.

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D Flip-Flop

Data flip-flop, no invalid state, transparent latch vs edge.

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D Latch

Level sensitive latch, transmission gate implementation.

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Code Converter Circuits