Up Down Counter

Up-down counters appear in motor speed controllers, position encoders, and audio volume logic where the count must increment or decrement under external control. A single direction pin switches the count mode without stopping the clock.

Core Concept

An up-down counter can increment or decrement depending on a control signal. The 74LS193 uses two separate clock pins: CLK_UP for counting up and CLK_DN for counting down. Whichever pin is held HIGH is inactive; pulsing the other advances the count.

The 74LS193 is a 4-bit presettable synchronous up-down counter. It has asynchronous clear (CLR) and asynchronous parallel load (LOAD_bar active low). Maximum clock frequency is 32 MHz. Propagation delay clock-to-output is 24 ns. Supply is 5 V and power consumption is 95 mW.

The CARRY_bar output goes low when the counter overflows from 1111 to 0000 during up-counting. The BORROW_bar output goes low when the counter underflows from 0000 to 1111 during down-counting. These two outputs allow direct cascading of multiple 74LS193s to build 8-bit or 12-bit up-down counters.

Boolean Expression

The carry output of the 74LS193 is CARRY_bar = NOT(QA·QB·QC·QD·CLK_UP_bar). It goes low when all outputs are 1 and the UP clock is low (about to transition). Similarly, BORROW_bar = NOT(QA_bar·QB_bar·QC_bar·QD_bar·CLK_DN_bar).

For T flip-flop implementation of a 4-bit up-down counter, the toggle inputs depend on mode. In UP mode: T_k = Q0·Q1·...·Q(k-1). In DOWN mode: T_k = Q0_bar·Q1_bar·...·Q(k-1)_bar. A MUX controlled by the UP/DOWN pin selects the correct expression for each stage.

Given:
Trace a 74LS193 up-down counter.
Start at 0011 (decimal 3). Count UP twice, then DOWN three times.

Formula / Rule:
UP: increment by 1 on each CLK_UP pulse (CLK_DN held HIGH)
DN: decrement by 1 on each CLK_DN pulse (CLK_UP held HIGH)
Wrap-around: 1111+1=0000 (carry), 0000-1=1111 (borrow)

Step by step:
Initial: 0011 = 3
UP pulse 1: 0011 -> 0100 = 4
UP pulse 2: 0100 -> 0101 = 5
DN pulse 1: 0101 -> 0100 = 4
DN pulse 2: 0100 -> 0011 = 3
DN pulse 3: 0011 -> 0010 = 2

Final Answer:
Sequence: 3 -> 4 -> 5 -> 4 -> 3 -> 2
No carry or borrow events occurred (count stayed within 0-15).

Exam Tip: The 74LS193 has two separate clock inputs, NOT a single clock plus direction pin. The inactive clock must be held HIGH, not LOW. If both clocks are pulsed simultaneously, the behavior is undefined. GATE questions may ask about CARRY_bar and BORROW_bar — remember both are active LOW and are used as clocks (not enables) for cascaded stages.

Key Properties

• 74LS193: 32 MHz max clock, 24 ns propagation delay, 5 V supply, 95 mW
• 74HC193: CMOS equivalent, 2–6 V supply, under 1 mW static, 50 MHz clock
• CARRY_bar active-low; goes low briefly when count rolls over from 15 to 0
• BORROW_bar active-low; goes low briefly when count rolls under from 0 to 15
• Asynchronous load: LOAD_bar low forces parallel data A,B,C,D into counter instantly
• Asynchronous clear: CLR high forces 0000 regardless of clock state
• Cascading: CARRY_bar of lower chip connects to CLK_UP of higher chip for multi-byte counters

Quick Revision

• Two separate clock inputs: CLK_UP and CLK_DN — inactive one held HIGH
• CARRY_bar pulses low on 15->0 transition during up-count
• BORROW_bar pulses low on 0->15 transition during down-count
• Preset any value: hold LOAD_bar low and apply data to A,B,C,D inputs
• Asynchronous CLR overrides everything — active HIGH
• Cascade: CARRY_bar -> CLK_UP of next stage for larger up counters
• 74LS191 is a single-clock up-down counter with UP/DOWN pin — different pinout
• Exam trap: Connecting CARRY_bar to CLK_DN (not CLK_UP) of the next stage — this causes wrong direction of cascaded count