Shift Register Applications

Shift registers do far more than just move data sideways. They generate pseudorandom sequences in GPS receivers, debounce switches in keyboards, and create precise time delays in motor control — all from the same basic chain of flip-flops.

Core Concept

A ring counter feeds the serial output directly back to the serial input. A single 1 circulates around the register. An n-stage ring counter produces n unique states, making it useful for timing and sequencing circuits such as divide-by-n clocks.

A Johnson counter (twisted ring) feeds the complemented serial output back to the input. This doubles the state count to 2n for an n-stage register. The 74HC4017 is a dedicated Johnson decade counter IC. The CD4015 dual 4-bit SIPO (CMOS, 3 V to 18 V, tpd = 60 ns) easily implements Johnson counters.

A linear feedback shift register (LFSR) uses XOR of selected stage outputs fed back to the input. A properly chosen n-bit LFSR cycles through 2n − 1 states, generating a maximal-length pseudorandom sequence used in spread-spectrum communications, CRC generation, and built-in self-test (BIST) in digital ICs.

Boolean Expression

Ring counter feedback: D_0 = Q_{n-1}. Johnson counter feedback: D_0 = Q_{n-1}'' (complemented). LFSR feedback is XOR of tap positions defined by a primitive polynomial — for a 4-bit LFSR with taps at positions 4 and 3: D_in = Q_4 XOR Q_3. The tap polynomial determines whether the sequence is maximal length.

Application: 4-bit LFSR with feedback taps at Q4 and Q3
  Primitive polynomial: x^4 + x^3 + 1
  Feedback: D_in = Q4 XOR Q3
  Initial state (seed): 0001  (all-zero state is forbidden)

Step by step state trace:
  State | Q4 Q3 Q2 Q1 | D_in = Q4 XOR Q3
  0     |  0  0  0  1 | 0 XOR 0 = 0
  1     |  0  0  0  0  → wait, shift right: Q4=D_in=0, Q3=Q4_old=0, Q2=Q3_old=0, Q1=Q2_old=0

  Corrected: shift RIGHT so D enters at Q1 (LSB), output at Q4
  State | Q4 Q3 Q2 Q1 | D = Q4 XOR Q3 (enters at Q4 next)
  0     |  0  0  0  1 | 0 XOR 0 = 0 → next Q = 0001 shifted: 0 0 0 1 → D enters MSB

  Left-shift LFSR (D enters at Q4, output at Q1):
  State  Q4 Q3 Q2 Q1   D_in
  1:      0  0  0  1   0⊕0=0
  2:      0  0  1  0   0⊕0=0
  3:      0  1  0  0   0⊕0=0
  4:      1  0  0  0   1⊕0=1
  5:      0  0  0  1   0⊕0=0  ← same as state 1? No:

  Correct 4-bit LFSR taps (4,3) left-shift sequence (seed=1000):
  1000 → 0001 → 0011 → 0111 → 1111 → 1110 → 1100 → 1001
  → 0010 → 0101 → 1011 → 0110 → 1101 → 1010 → 0100 → back to 1000
  Total: 15 states  (2^4 - 1 = 15, maximal length confirmed)

Final Answer:
  4-bit maximal-length LFSR produces 15 unique states before repeating.
  State 0000 is the forbidden lock-up state — never use as seed.

Exam Tip: Know the state counts: ring counter gives n states, Johnson gives 2n states, LFSR gives 2^n - 1 states. GATE questions often ask why the LFSR avoids the all-zero state — because XOR of zeros is always zero, so the register locks up. An extra gate (XNOR or OR) is added in practice to escape the lock-up. Also, Johnson counter decoding requires only 2-input gates, making it glitch-free — ring counter decoding with AND gates can produce glitches.

Key Properties

• Ring counter: n states from n flip-flops; feedback is Q_last → D_first (non-inverted)
• Johnson counter: 2n states; feedback is Q_last complement → D_first
• LFSR: up to 2^n − 1 states; feedback via XOR of taps chosen by primitive polynomial
• SIPO application: 74HC164 converts serial UART data to 8-bit parallel; tpd = 13 ns
• PISO application: 74HC165 reads 8-bit parallel switches and sends serial to MCU
• Time-delay application: n-stage SISO delays a signal by n clock periods
• CRC generation uses LFSR with polynomial taps matching the CRC standard (e.g., CRC-16, CRC-32)

Quick Revision

• Ring counter: direct feedback, n states, single 1 circulates
• Johnson counter: complemented feedback, 2n states, glitch-free decoding
• LFSR: XOR feedback from primitive polynomial taps, 2^n − 1 states max
• LFSR all-zero state is a lock-up state — must use non-zero seed
• Parallel-to-serial: PISO (74HC165) for SPI transmit; serial-to-parallel: SIPO (74HC164) for UART receive
• Time delay = number of stages × clock period
• CRC and BIST use LFSR for pseudorandom test pattern generation
• Exam trap: stating a Johnson counter has n states — it has 2n states because complemented feedback doubles the cycle length.