PISO Shift Register

Every UART and SPI peripheral uses a shift register to move data one bit at a time. The Parallel-In Serial-Out (PISO) shift register loads a full data word in one clock cycle and then shifts it out bit by bit — exactly what your microcontroller does when it sends a byte over SPI.

Core Concept

A PISO register loads all input bits simultaneously when the shift/load (SH/LD) control pin is LOW. On the very next clock cycle, the register enters shift mode and pushes bits out from the most significant position one by one.

The 74HC165 is the standard 8-bit PISO IC. It runs from 2 V to 6 V, has a propagation delay of about 14 ns at 5 V, and offers a fan-out of 10 LSTTL loads. It has a complementary output Q and its shift direction is always right (toward Q).

PISO registers convert parallel data — like an 8-bit port reading — into a serial stream for transmission. This is why they appear in ADC readout circuits, keyboard scan logic, and SPI shift chains in embedded systems.

Boolean Expression

During load: each flip-flop receives its parallel input Dn directly. During shift: each stage passes its state to the next. The characteristic equation for each stage is Q(t+1) = SH/LD' · Dn + SH/LD · Q_prev(t). When SH/LD is LOW the first term dominates (load); when SH/LD is HIGH the second term dominates (shift).

Given:
  4-bit PISO register, initial parallel input D3 D2 D1 D0 = 1 0 1 1
  SH/LD goes LOW for 1 clock, then HIGH for 4 clocks
  Serial input (SI) = 0

Formula / Rule:
  Load cycle : Q3 Q2 Q1 Q0 = D3 D2 D1 D0
  Shift cycle : each Qn gets value of Qn+1; Q3 gets SI

Step by step:
  After load  (CLK1, SH/LD=0) : Q3=1  Q2=0  Q1=1  Q0=1   Serial Out = Q0 = 1
  After CLK2  (SH/LD=1)       : Q3=0  Q2=1  Q1=0  Q0=1   Serial Out = 1
  After CLK3  (SH/LD=1)       : Q3=0  Q2=0  Q1=1  Q0=0   Serial Out = 0  (wait — Q0 after shift)

  Corrected trace (MSB first out means Q3 exits first):
  74HC165 shifts so that D7(MSB) comes out first.
  Restate for 4-bit: D3 exits first.

  CLK1 load : register = 1 0 1 1  (D3 to D0)
  CLK2 shift: Serial Out = 1 (D3); register = 0 1 0 1  (SI shifted in at D3)
  CLK3 shift: Serial Out = 0 (D2); register = 0 0 1 0
  CLK4 shift: Serial Out = 1 (D1); register = 0 0 0 1
  CLK5 shift: Serial Out = 1 (D0); register = 0 0 0 0

Final Answer:
  Serial output sequence (MSB first): 1, 0, 1, 1
  This matches the original parallel word D3 D2 D1 D0 = 1011

Exam Tip: GATE often asks which bit exits first in a PISO register. The answer is the MSB (D3 or D7 depending on width) because the register shifts right and the highest-index flip-flop feeds the output pin. Do not confuse PISO with SIPO — in SIPO the data enters serially and appears at parallel outputs. The 74HC165 also has an active-LOW parallel load, so SH/LD=0 means LOAD, not shift — many students get this backwards.

Key Properties

• IC 74HC165: 8-bit PISO, Vcc = 2 V to 6 V, tpd = 14 ns typical at 5 V
• Fan-out: 10 LSTTL loads; power dissipation under 80 µW at 1 MHz (CMOS quiescent)
• Parallel load is level-triggered on SH/LD (asynchronous in 74HC165); shift is clocked
• Serial data input (SI) is shifted into the MSB position during each shift clock
• 4-bit equivalent: 74HC194 in PISO mode; 8-bit: 74HC165 or CD4021B (CMOS)
• Conversion time for n bits = n clock periods; useful for parallel-to-serial interface
• Logic family comparison: 74HC165 (CMOS, low power) vs 74LS165 (TTL, 20 mA supply)

Quick Revision

• PISO = Parallel-In Serial-Out; loads all bits at once, shifts out one bit per clock
• SH/LD = 0 → load mode; SH/LD = 1 → shift mode (active-LOW load in 74HC165)
• MSB exits first because the register shifts right toward the serial output pin
• Serial input (SI) fills the MSB position vacated during each shift
• 74HC165 is 8-bit PISO; 4-bit PISO available in 74HC194 universal register
• Main application: converting parallel port data to serial stream for SPI/UART
• Conversion latency = n clock cycles for n-bit word
• Exam trap: students write LSB exits first — wrong. In a standard right-shift PISO the MSB (highest parallel input) exits first.