XOR Gate

The XOR gate (Exclusive OR gate) is a fundamental logic gate that produces a HIGH output only when its inputs are different. Unlike the standard OR gate which outputs HIGH when any input is HIGH, XOR specifically checks for inequality between inputs, making it uniquely useful in arithmetic circuits, error detection, and comparators.

XOR gate behavior appears repeatedly in GATE examination problems related to adders, parity generators, and Boolean simplification. The IC 7486 is the standard TTL implementation. Understanding XOR at the expression, truth table, and application level is essential for digital electronics.

Core Concept: What XOR Gate Does

The XOR gate compares its two inputs and outputs HIGH only when they are different. When A and B are the same (both 0 or both 1), the output is LOW. When A and B are different (one is 0 and the other is 1), the output is HIGH. This inequality-detection property is what makes XOR fundamentally different from the basic OR gate.

Physically, in TTL implementation, the XOR gate is constructed using a combination of AND, OR, and NOT gates internally. It cannot be built with a single transistor pair like a NAND or NOR gate; it requires a more complex circuit. This is why XOR gates have slightly higher propagation delay compared to basic gates in the same IC family.

The XOR operation is often described as modulo-2 addition. In binary arithmetic, 0+0=0, 0+1=1, 1+0=1, and 1+1=0 (with a carry, but ignoring the carry). These results exactly match the XOR truth table. This connection to binary addition makes XOR the foundation of all digital adder circuits.

Mathematical Expression

The Boolean expression for a 2-input XOR gate is:

Y = A xor B = A'B + AB'

This expanded form shows that Y is HIGH when A is LOW and B is HIGH (term A'B), or when A is HIGH and B is LOW (term AB'). An alternative form is Y = (A + B)(A' + B'), which can be verified by expanding and simplifying. The canonical SOP form A'B + AB' is particularly useful in Karnaugh map-based simplification and identifying XOR patterns in complex expressions.

Key identity: A xor A = 0, A xor 0 = A, A xor 1 = A'. These three identities are frequently tested in GATE. They allow simplification of complex XOR chains. For example, A xor A xor B = 0 xor B = B. This kind of telescopic cancellation appears in parity and error detection problems.

Practical Understanding: Applications of XOR

The most fundamental application of XOR is in the half adder circuit. A half adder takes two single-bit inputs A and B and produces a Sum bit (S = A xor B) and a Carry bit (C = A . B). The XOR gate directly computes the sum bit, while an AND gate computes the carry. This simple two-gate combination forms the building block of all binary adders.

XOR is also used in parity generators and checkers. An even parity bit for a data word is computed by XORing all data bits together. If the XOR of all bits is 0, the number of 1s is even (even parity). This is used in UART communication protocols, RAID storage parity, and memory error detection. IC 74180 is a dedicated 8-bit parity generator using XOR logic.

IC 7486 provides four independent 2-input XOR gates in a 14-pin DIP package. It operates at 5V VCC with a typical propagation delay of about 14 ns, which is slightly higher than basic NAND or NOR gates due to the more complex internal circuit. XOR is also central to comparators (two bits are equal when XOR output is 0) and to cryptographic circuits where XOR is used for key mixing.

Numerical Example

Consider a 3-bit parity generator circuit. Given data bits D2=1, D1=0, D0=1, calculate the even parity bit P using cascaded XOR gates, and verify the final 4-bit word has even parity.

Given:
Data bits: D2 = 1, D1 = 0, D0 = 1
Requirement: Even parity bit P such that total number of 1s in (D2, D1, D0, P) is even

Why this formula applies:
Parity is computed by XORing all data bits. Even parity: P = D2 xor D1 xor D0

Formula:
P = D2 xor D1 xor D0

Substitution:
P = 1 xor 0 xor 1

Calculation:
Step 1: 1 xor 0 = 1
Step 2: 1 xor 1 = 0
P = 0

Verification:
4-bit word: D2 D1 D0 P = 1 0 1 0
Number of 1s = 2 (even) -> Even parity confirmed

Final Answer with units:
Even Parity bit P = 0 (Logic LOW)
4-bit transmitted word = 1010 with even parity verified

Exam Tip: XOR output is 1 when inputs are different and 0 when inputs are the same. Remember the identity A xor A = 0 and A xor 0 = A. In GATE, XOR chains can be simplified quickly by cancelling identical pairs. Parity of n bits equals the XOR of all n bits.

• Y = A xor B = A'B + AB': output HIGH only when inputs differ, which is the exclusive OR.
• Modulo-2 addition property makes XOR the sum bit of a half adder circuit directly.
• Key identities: A xor A = 0, A xor 0 = A, A xor 1 = A'. Used in GATE simplification.
• Parity generator: XOR of all data bits gives the parity bit for error detection in communication.
• IC 7486: Quad 2-input XOR gate, 14-pin DIP, TTL, VCC = 5V, ~14 ns propagation delay.

Quick Revision

• XOR expression: Y = A xor B = A'B + AB'. Output is 1 when inputs are different.
• Truth table: Outputs 1 for combinations (0,1) and (1,0) only. Same inputs always give 0.
• Key identities: A xor A = 0, A xor 0 = A, A xor 1 = A'. Memorize for GATE.
• Half adder: Sum = A xor B, Carry = A.B. XOR directly gives the sum bit.
• Parity: Even parity bit = XOR of all data bits. If XOR = 0, parity is even.
• IC 7486: Quad 2-input XOR, 5V TTL, four gates per IC, ~14 ns delay.
• Exam trap: XOR is NOT a universal gate. It cannot implement AND or OR by itself without additional gates.