Asynchronous Counter
Ripple counter, propagation delay accumulation.
Asynchronous Counter Quiz
Challenge yourself on ripple counter propagation delay and modulus design.
Question 1 of 3
Q1.A 4-bit ripple counter uses four T flip-flops, each with a propagation delay of 10 ns. What is the worst-case delay from the clock edge to a valid output at Q3 (MSB)?
Related Articles
BCD Counter
Mod-10 counter, 0000 to 1001, auto reset.
8 min read
Johnson Counter
Twisted ring counter, 2N states from N flip-flops.
8 min read
Mod-N Counter
Arbitrary modulus counter design, feedback reset logic.
11 min read
Ring Counter
Circular shift register, one-hot state encoding.
12 min read
Up Down Counter
Bidirectional counting, control input for direction.
4 min read