4-to-1 Multiplexer

A 4-to-1 multiplexer is the building block of every FPGA lookup table and data bus switch. It routes one of four input data lines to a single output based on a 2-bit select code, making it the simplest multi-input MUX used in real designs.

Core Concept

A 4-to-1 multiplexer has four data inputs (I0–I3), two select inputs (S1, S0), and one output Y. The 2-bit select code acts like a 2-bit binary number: S1S0 = 00 routes I0, S1S0 = 01 routes I1, S1S0 = 10 routes I2, and S1S0 = 11 routes I3. Think of it as a digitally controlled switch.

Internally the MUX uses AND-OR logic: each data input is ANDed with its unique minterm of S1 and S0, and the four AND outputs are ORed together. The 74153 is a dual 4:1 MUX in a 16-pin DIP package. It includes an active-low enable (strobe) input that forces Y low when deasserted, useful for cascading.

The 74LS153 version operates from 5 V with a propagation delay of about 22 ns and a fan-out of 20 in LS-TTL. The CMOS 74HC153 runs from 2 V to 6 V, draws under 80 µA static, and has a propagation delay of 15 ns at 4.5 V — preferred in battery-powered systems.

Boolean Expression

The output is Y = S1'S0'I0 + S1'S0I1 + S1S0'I2 + S1S0I3. Each term is a minterm of S1, S0 ANDed with one data input. This makes the MUX a natural function generator: fixing the data inputs to 0 or 1 implements any 2-variable Boolean function of S1 and S0, or any 3-variable function when one select input is replaced by a third variable.

Given:
  4:1 MUX with I0=1, I1=0, I2=1, I3=1
  Select: S1=1, S0=0

Formula / Rule:
  Y = S1'S0'·I0 + S1'S0·I1 + S1S0'·I2 + S1S0·I3

Step by step:
  S1=1, S0=0:
  Term 1: S1'S0' = 0·1 = 0  → 0·I0 = 0
  Term 2: S1'S0  = 0·0 = 0  → 0·I1 = 0
  Term 3: S1S0'  = 1·1 = 1  → 1·I2 = 1·1 = 1
  Term 4: S1S0   = 1·0 = 0  → 0·I3 = 0

  Y = 0 + 0 + 1 + 0 = 1

Verification:
  S1S0 = 10 → select I2; I2 = 1; Y = 1  ✓

Final Answer:
  Y = 1  (I2 is routed to output)

Exam Tip: GATE loves the MUX-as-function-generator question. A 4:1 MUX can implement any 3-variable Boolean function of variables A, B, C by connecting A and B to the select lines and applying appropriate values of C, C', 0, or 1 to the data inputs. Map the truth table of the desired function: for each pair of values of A,B, find what the function output must be for C=0 and C=1, then determine the data input expression (0, 1, C, or C') that matches both rows.

Key Properties

• 74153: dual 4:1 MUX, 5 V TTL, propagation delay 22 ns (LS), fan-out 20.
• 74HC153: CMOS version, 2–6 V supply, 15 ns at 4.5 V, ultra-low static power.
• Active-low enable pin forces output low, enabling easy cascading of multiple 4:1 MUXes.
• Implements any 2-variable Boolean function directly; any 3-variable function with one variable on data inputs.
• CD4052 is a CMOS analog 4:1 MUX that handles analog signals up to ±7.5 V (unlike digital-only 74 series).
• Two 4:1 MUXes plus a 2:1 MUX build an 8:1 MUX using the enable pins.
• Internal structure: four AND gates (3-input each) and one 4-input OR gate.

Quick Revision

• 4 data inputs, 2 select lines, 1 output.
• S1S0 = 00→I0, 01→I1, 10→I2, 11→I3.
• Y = Σ (Si minterm · Ii) for i = 0 to 3.
• 74153 has active-low enable; output low when enable is high.
• Implements any Boolean function of 2 select variables.
• One extra variable on data inputs extends to 3-variable function generation.
• Cascade two 4:1 MUXes with a 2:1 to build 8:1.
• Exam trap: thinking that S1S0 = 10 selects I1 — it selects I2 because S1 is the MSB, so binary 10 = decimal 2.