Flip-Flop Conversions

Every digital system needs flip-flops, but not always the same kind. Flip-flop conversion lets you build any flip-flop type from another, which is exactly how IC designers reuse silicon and how GATE examiners test whether you truly understand sequential logic.

Core Concept

A flip-flop conversion finds the combinational logic needed at the inputs of a given flip-flop so it behaves like a target flip-flop. You start from the excitation table of the flip-flop you have, then derive input equations using a K-map.

The 74LS76 is a dual JK flip-flop in DIP-16. Its propagation delay is 20 ns typical at 5 V. The 74LS74 is the standard D flip-flop with 25 ns propagation delay and a fan-out of 20 in LS TTL. Both are 5 V devices drawing under 20 mW at full speed.

Every conversion follows three steps: write the excitation table of the available flip-flop, list the present-state and next-state columns for each row, then fill K-maps for each required input. Don't skip the don't-care entries — they simplify the result.

Boolean Expression

For JK-to-D conversion, the excitation table gives J = D and K = D-bar. This is because a D flip-flop must set when D=1 and reset when D=0, which maps exactly to J=D and K=D-bar after K-map simplification with don't-cares.

For D-to-JK conversion, the target is the characteristic equation Q(t+1) = J·Q-bar + K-bar·Q. Matching this to Q(t+1) = D gives D = J·Q-bar + K-bar·Q directly.

Given:
Convert a JK flip-flop to behave as a T flip-flop.

Formula / Rule:
T FF characteristic equation: Q(t+1) = T XOR Q(t)
JK FF excitation table:
  Q(t)->Q(t+1): 0->0: J=0,K=X  | 0->1: J=1,K=X
                1->0: J=X,K=1  | 1->1: J=X,K=0

Step by step:
1. T=0, Q=0 => Q(t+1)=0 => J=0, K=X
2. T=0, Q=1 => Q(t+1)=1 => J=X, K=0
3. T=1, Q=0 => Q(t+1)=1 => J=1, K=X
4. T=1, Q=1 => Q(t+1)=0 => J=X, K=1

K-map for J (rows=T, cols=Q):
  T=0,Q=0: 0 | T=0,Q=1: X
  T=1,Q=0: 1 | T=1,Q=1: X
  Simplify: J = T

K-map for K:
  T=0,Q=0: X | T=0,Q=1: 0
  T=1,Q=0: X | T=1,Q=1: 1
  Simplify: K = T

Final Answer:
J = T,  K = T
Connect input T directly to both J and K terminals.

Exam Tip: The most common mistake is applying the target flip-flop's excitation table instead of the available one. Always build the K-map using the rows of the flip-flop you physically have. Don't-care entries (X) are mandatory — omitting them gives a more complex expression and loses marks. In GATE problems, SR-to-D conversion has the extra constraint S=R=0 forbidden, which adds a don't-care row.

Key Properties

• 74LS76 JK FF: propagation delay 20 ns, fan-out 20, supply 5 V, power 40 mW
• 74LS74 D FF: propagation delay 25 ns, fan-out 20, supply 5 V, power 17 mW
• 74HC74 CMOS D FF: propagation delay 18 ns at 5 V, supply 2–6 V, power under 1 mW static
• JK to T conversion needs only one wire: J = K = T. No extra gates required.
• D to JK conversion needs one AND gate and one OR gate to form D = J·Q-bar + K-bar·Q
• SR to D conversion: S = D, R = D-bar; undefined state S=R=1 never occurs
• Conversion always adds combinational delay in front of the flip-flop clock-to-Q path

Quick Revision

• Use the excitation table of the available (given) flip-flop, not the target
• Fill K-maps for each input of the available flip-flop separately
• Don't-care entries from the excitation table must be carried into K-maps
• JK to T: J = T, K = T (simplest conversion, zero extra logic)
• JK to D: J = D, K = D-bar (one inverter required)
• D to JK: D = J·Q-bar + K-bar·Q (one AND, one OR, one inverter)
• SR FF has a forbidden state; treat S=R=1 rows as don't-cares in conversion K-maps
• Exam trap: Using the target FF's excitation table (instead of the available FF's) is the single most penalised error in GATE flip-flop conversion questions