Universal Shift Register

One IC that can act as SISO, SIPO, PISO, or PIPO depending on two control pins is the universal shift register. The 74HC194 is built into the ALU input stages of older 8-bit CPUs and is still used in FPGA prototype boards for flexible data routing.

Core Concept

The 74HC194 implements all four shift register modes using a 2-bit mode select (S1, S0). The mode is sampled on the rising clock edge, so the register can change behaviour every cycle without rewiring.

In shift-right mode (S1=0, S0=1), data moves from Q3 toward Q0 and a serial bit enters at the SR pin. In shift-left mode (S1=1, S0=0), data moves from Q0 toward Q3 and a serial bit enters at SL. Parallel load (S1=1, S0=1) captures all four D inputs simultaneously. Hold (S1=0, S0=0) freezes the register with no change.

The 74HC194 runs from 2 V to 6 V and has a propagation delay of 14 ns at 5 V. It provides four parallel outputs (Q0–Q3), a serial right output at Q3, and a serial left output at Q0. Two cascaded 74HC194s form an 8-bit universal register.

Boolean Expression

The characteristic equation for each stage Qi is the multiplexer expression Q_i(t+1) = S1''S0'' · Q_i + S1''S0 · Q_{i+1} + S1·S0'' · Q_{i-1} + S1·S0 · D_i. Each mode select pair steers one of four inputs: the held value, the right-shift neighbour, the left-shift neighbour, or the parallel data input.

Given:
  74HC194, initial state Q3 Q2 Q1 Q0 = 0 0 0 0
  SR (serial right input) = 1
  D3 D2 D1 D0 = 1 0 1 1

Sequence of operations:
  CLK1: S1=1, S0=1  → Parallel Load
  CLK2: S1=0, S0=1  → Shift Right (SR=0)
  CLK3: S1=0, S0=1  → Shift Right (SR=0)
  CLK4: S1=1, S0=0  → Shift Left  (SL=1)
  CLK5: S1=0, S0=0  → Hold

Step by step:
  After CLK1 (Load)         : Q3 Q2 Q1 Q0 = 1 0 1 1
  After CLK2 (Shift R, SR=0): Q3 Q2 Q1 Q0 = 0 1 0 1  (0 enters at Q3)
  After CLK3 (Shift R, SR=0): Q3 Q2 Q1 Q0 = 0 0 1 0  (0 enters at Q3)
  After CLK4 (Shift L, SL=1): Q3 Q2 Q1 Q0 = 0 1 0 1  (1 enters at Q0)
  After CLK5 (Hold)         : Q3 Q2 Q1 Q0 = 0 1 0 1  (no change)

Final Answer:
  Final state = 0101
  Hold mode preserves the register state indefinitely until mode changes.

Exam Tip: The most common GATE trap on universal registers is confusing which serial input is used in which shift direction. Shift-right uses SR (enters at Q3, MSB side). Shift-left uses SL (enters at Q0, LSB side). Also, S1=S0=0 is HOLD, not reset — the state is frozen, not cleared. Asynchronous CLR (active LOW) is the only way to force all zeros without a clock edge.

Key Properties

• IC 74HC194: 4-bit universal, Vcc = 2 V to 6 V, tpd = 14 ns, fan-out = 10 LSTTL
• Four modes: Hold (00), Shift Right (01), Shift Left (10), Parallel Load (11)
• Two independent serial inputs: SR for right-shift, SL for left-shift
• Parallel outputs Q0–Q3 available simultaneously in all modes
• Active-LOW asynchronous CLR resets all flip-flops immediately
• Two 74HC194s cascade easily to form an 8-bit universal register
• CMOS logic family; 74LS194 (TTL) equivalent draws 75 mW vs µW for HC version

Quick Revision

• Universal register: all four shift register modes selectable via S1 S0 every clock
• S1S0 = 00 Hold, 01 Shift Right, 10 Shift Left, 11 Parallel Load
• Shift right: data moves Q3→Q2→Q1→Q0; SR bit enters at Q3
• Shift left: data moves Q0→Q1→Q2→Q3; SL bit enters at Q0
• Characteristic equation is a 4-to-1 mux per stage driven by S1 and S0
• 74HC194 is 4-bit; cascade two for 8-bit; connect Q0 of one to SL of next for left-shift chain
• CLR is asynchronous and active LOW — does not wait for clock
• Exam trap: mixing up SR and SL inputs — SR is for right shift (enters at MSB), SL is for left shift (enters at LSB).