Binary Multiplier

Binary multiplication appears in every DSP filter, graphics shader, and floating-point unit. Hardware multipliers use a shift-and-add array structure that computes all partial products simultaneously, avoiding the slow sequential loop of software multiplication.

Core Concept

A binary multiplier implements the same long multiplication taught in primary school but in base 2. Each bit of the multiplier B, when 1, selects the multiplicand A shifted left by the corresponding bit position. These shifted copies are called partial products and their sum is the final product.

In an array multiplier, all partial products are generated simultaneously using AND gates: bit AiBj = Ai AND Bj. An n×n multiplier needs n² AND gates for the partial products and then a triangle of adders to sum the partial product array. The result is 2n bits wide for two n-bit inputs.

The 74284 and 74285 are TTL 4-bit×4-bit parallel multiplier ICs that together produce an 8-bit product. They operate from 5 V with a propagation delay of about 40 ns. Modern FPGAs embed dedicated DSP slices that multiply 18-bit or 27-bit operands in a single clock cycle at 300 MHz+ using a pipelined Wallace tree architecture.

Boolean Expression

Each partial product bit is PPij = Ai AND Bj. The product bit Pk is the sum of all partial product bits in column k plus carries from column k-1. For a 2×2 multiplier: P0 = A0B0; P1 = A1B0 XOR A0B1; P2 = A1B1 XOR carry; P3 = final carry. For larger multipliers the column sums are handled by a ripple adder array or, for speed, a Wallace tree of carry-save adders.

Given:
  Multiply A = 1101 (13) by B = 1011 (11)
  Expected product = 143 = 10001111

Formula / Rule:
  PPij = Ai AND Bj
  Align partial products by bit weight and sum.

Step by step:
  B0=1: PP0 = 1×1101 = 0001101  (shift 0)
  B1=1: PP1 = 1×1101 = 0011010  (shift 1)
  B2=0: PP2 = 0×1101 = 0000000  (shift 2)
  B3=1: PP3 = 1×1101 = 1101000  (shift 3)

  Sum the partial products:
      0001101
      0011010
      0000000
    + 1101000
    ---------
    Step: 0001101 + 0011010 = 0100111
          0100111 + 0000000 = 0100111
          0100111 + 1101000 = 10001111

Final Answer:
  Product = 10001111 = 143 in decimal  ✓
  (8-bit result for two 4-bit inputs)

Exam Tip: GATE problems ask for the number of AND gates and adders in an n×n array multiplier. AND gates = n², since every Ai is ANDed with every Bj. The first partial product row needs no adder (it feeds the adder array directly). You need (n-1) rows of adders, each row containing n full adders. For a 4×4 multiplier: 16 ANDs and 3 rows of 4 full adders = 12 full adders (some replaced with half adders at row edges). The product is always 2n bits wide.

Key Properties

• n×n multiplier produces a 2n-bit product; n² AND gates for partial products.
• Array multiplier uses (n-1) adder rows; delay is O(n) due to the adder chain.
• Wallace tree reduces delay to O(log n) by using carry-save adders and summing three rows to two simultaneously.
• 74284/74285 pair: TTL 4×4 multiplier, 5 V, ~40 ns propagation delay.
• FPGA DSP48 slice: 18×18 signed multiplier, 1 clock cycle at 450 MHz in 7-series Xilinx.
• Booth encoding reduces the number of partial products by half for signed multiplication.
• Power consumption scales as O(n²) with operand width in naive array design.

Quick Revision

• PPij = Ai AND Bj; n² AND gates for n-bit operands.
• Partial products aligned by bit weight, then summed.
• Product is always 2n bits wide.
• Array multiplier delay: O(n); Wallace tree delay: O(log n).
• 74284 + 74285 produce 8-bit product from two 4-bit inputs.
• Booth encoding reduces partial products for signed numbers.
• First partial product row feeds adder array directly; no adder needed for row 0.
• Exam trap: counting (n-1) adder rows but forgetting that each row has n full adder cells, not n-1 — the MSB column also needs a full adder to handle the carry chain.