CPLD

The CPLD — Complex Programmable Logic Device — sits between a PAL and an FPGA in the programmable logic hierarchy. It powers glue logic in hard drives, keyboards, and industrial controllers where deterministic timing is mandatory.

Core Concept

A CPLD integrates multiple PAL-like macrocell blocks on one chip, connected by a global programmable interconnect called the PIA (Programmable Interconnect Array) or switch matrix. Each macrocell block contains an AND array, a fixed OR gate, and a D flip-flop with output polarity control. The global routing fabric connects any macrocell output to any other macrocell's AND array input.

Altera's MAX7000 family is the classic CPLD. The MAX7128S has 128 macrocells, 5 ns pin-to-pin propagation delay, and runs at 3.3 V. It is EEPROM-based (electrically erasable, reprogrammable) and retains configuration without power — a key advantage over SRAM-based FPGAs.

Xilinx CoolRunner-II is a CMOS CPLD family designed for low power. It uses XPLA3 architecture with a central AIM (Advanced Interconnect Matrix) routing fabric. Standby current is under 10 µA, making it ideal for battery-powered devices. CPLDs offer deterministic timing that FPGAs cannot always guarantee because CPLD routing delays are predictable from the datasheet.

Boolean Expression

Each CPLD macrocell output follows the PAL equation: F = (P1 + P2 + ... + Pk) XOR POL where POL is a programmable polarity bit. The XOR with POL lets the user invert the output without adding an external inverter, effectively doubling the expressible functions per macrocell. Registered macrocells additionally pass the OR output through a D flip-flop clocked by the global or local clock network.

Given:
  CPLD MAX7128S macrocell
  Implement 3-bit up counter using 3 macrocells with D flip-flops
  States: 000→001→010→011→100→101→110→111→000

Formula / Rule:
  D flip-flop: Q(t+1) = D
  For binary counter bit i: D_i = Q_i XOR (Q_{i-1} AND Q_{i-2} AND ... AND Q_0)

Step by step:
  D0 = Q0' (toggle every clock)
  D1 = Q1 XOR Q0
  D2 = Q2 XOR (Q1·Q0)

  Macrocell 1 (Q0): AND plane programs D0=Q0', flip-flop clocked by global CLK
  Macrocell 2 (Q1): AND plane programs Q1'·Q0 + Q1·Q0' (=Q1 XOR Q0), flip-flop clocked
  Macrocell 3 (Q2): AND plane programs Q2 XOR (Q1·Q0), flip-flop clocked

  PIA connects Q0,Q1,Q2 back into AND planes of all three macrocells

Final Answer:
  3 macrocells implement full 3-bit binary counter.
  Pin-to-pin delay: 5 ns. Max clock frequency: ~166 MHz (MAX7128S-5).

Exam Tip: GATE distinguishes CPLD from FPGA on three points: (1) CPLD uses EEPROM/flash — retains config at power-off; FPGA uses SRAM — loses config at power-off and needs a boot ROM. (2) CPLD has predictable fixed routing delay; FPGA routing delay varies with placement. (3) CPLD is better for wide, flat logic (lots of inputs, few outputs); FPGA is better for deep pipelined logic or large designs. Do not say CPLDs cannot do sequential logic — registered macrocells include D flip-flops.

Key Properties

• Architecture: multiple PAL macrocell blocks + global switch matrix (PIA/AIM)
• Altera MAX7128S: 128 macrocells, 5 ns pin-to-pin delay, 3.3 V, EEPROM non-volatile
• Xilinx CoolRunner-II XC2C32A: 32 macrocells, <10 µA standby, 1.8 V core, ideal for IoT
• Configuration: EEPROM or flash-based — no external boot ROM needed, instant power-up
• Fan-out: I/O pins typically drive 24 mA (3.3 V); internal macrocells drive the full PIA fabric
• Propagation delay: predictable from datasheet (e.g., 5 ns), unlike FPGA routing which depends on P&R
• Typical capacity: 32 to 512 macrocells; above 512 macrocells, designers move to FPGA

Quick Revision

• CPLD = multiple PAL-like macrocell blocks connected by programmable routing (PIA)
• Macrocell = AND array + fixed OR + D flip-flop + polarity XOR
• EEPROM-based: retains configuration without power (unlike SRAM-based FPGA)
• Deterministic timing: routing delay is fixed and predictable — critical for glue logic
• Altera MAX7000, Xilinx XC9500, Lattice ispMACH are major CPLD families
• Capacity: 32-512 macrocells; suits medium-complexity combinational + sequential logic
• Exam trap: students claim CPLDs cannot implement sequential circuits — macrocells include D flip-flops, so sequential logic is fully supported