SR Flip-Flop

While the gated SR latch is level-sensitive and responds to inputs throughout the enable period, practical synchronous systems require state changes to occur only at the precise instant of a clock edge. The SR flip-flop is an edge-triggered bistable device that samples S and R inputs only at the active clock transition (rising or falling edge) and is immune to input changes at all other times. This makes it a truly synchronous memory element suitable for use in registers, counters, and finite state machines.

Core Concept: Edge Triggering

The fundamental difference between a latch and a flip-flop is the triggering mechanism. A latch is level-sensitive and responds throughout the enable duration. A flip-flop is edge-triggered and responds only at the instant of the clock edge. In a positive edge-triggered SR flip-flop, the S and R inputs are sampled only at the rising edge of the clock. Between clock edges, the output is completely locked regardless of input changes.

Edge triggering is implemented using a master-slave configuration of two gated latches. The master latch captures the input during the first half of the clock cycle, and the slave latch transfers the captured value to the output on the clock edge. This two-stage structure ensures that only the values present at the exact clock edge are stored, eliminating the transparency problem of simple gated latches.

Characteristic Equation and Excitation Table

The characteristic equation of the SR flip-flop describes the next state as a function of current inputs and current state: Q(t+1) = S + R' Q(t), subject to the constraint SR = 0. This is the same form as the SR latch but now applies only at the clock edge. The constraint SR=0 means S and R must not simultaneously be 1.

The excitation table is the inverse of the characteristic table. Instead of telling what the next state will be given S and R, it tells what S and R must be applied to achieve a desired state transition. The excitation table is essential for designing sequential circuits using SR flip-flops.

In the excitation table, X represents a don't care condition. For example, if the current state is Q=0 and we want Q(t+1)=0 (no change), S must be 0 but R can be anything (0 or 1) because R only matters when Q=1. This don't care simplification reduces hardware in sequential circuit design.

Practical Understanding

SR flip-flops are less commonly used in practice compared to D or JK flip-flops, primarily because the forbidden state S=R=1 must always be avoided by the designer. However, understanding the SR flip-flop is fundamental for GATE because the excitation table and characteristic equation concepts are directly tested. The SR flip-flop is also a useful starting point for deriving the JK flip-flop, which eliminates the forbidden state.

In synchronous counter design, the excitation table is used to determine what inputs must be applied to each flip-flop at each count step. The don't care conditions in the SR excitation table often result in simpler logic compared to using D flip-flops, making SR-based designs occasionally preferable when minimizing gate count.

Given:
SR flip-flop, positive edge-triggered.
Design a 2-bit synchronous up-counter using SR flip-flops.
Current state Q1Q0 = 01 (decimal 1). Find required S and R for each flip-flop to go to Q1Q0 = 10 (decimal 2).

Why this formula applies:
Excitation table: For transition 0→1: S=1,R=0. For transition 1→0: S=0,R=1. For 0→0: S=0,R=X. For 1→1: S=X,R=0.

Formula:
Use excitation table to find S and R for each bit.

Substitution:
Q0 transition: 1 → 0  (current Q0=1, next Q0=0)
  From excitation table: S0=0, R0=1

Q1 transition: 0 → 1  (current Q1=0, next Q1=1)
  From excitation table: S1=1, R1=0

Calculation:
At the next clock edge:
  Apply S1=1, R1=0 to FF1 → Q1 goes to 1
  Apply S0=0, R0=1 to FF0 → Q0 goes to 0

Final Answer:
Required inputs at clock edge: S1=1, R1=0, S0=0, R0=1
Next state after edge: Q1Q0 = 10 (decimal 2). Correct.

Exam Tip: The SR flip-flop characteristic equation is Q(t+1) = S + R'Q with constraint SR=0. In excitation table, transition 0→0 gives S=0,R=X and transition 1→1 gives S=X,R=0. These don't cares are frequently exploited in GATE counter design questions.

Quick Revision

• SR flip-flop is edge-triggered: samples S and R only at the active clock edge, not during entire clock period.
• Characteristic equation: Q(t+1) = S + R'Q(t), constraint SR=0.
• Excitation table: 0→0: S=0,R=X; 0→1: S=1,R=0; 1→0: S=0,R=1; 1→1: S=X,R=0.
• Forbidden state S=R=1 leaves next state undefined; must always be avoided in design.
• Implemented as master-slave latch pair; master captures on one clock phase, slave transfers on the edge.
• Exam trap: SR flip-flop has don't care in excitation table (X values) which reduce logic in counter design. Do not treat X as 0 or 1 always; use it to simplify K-maps.
• JK flip-flop is SR flip-flop with J=S, K=R and added feedback that handles J=K=1 by toggling, eliminating forbidden state.