Johnson Counter

Johnson counters, also called twisted-ring counters, double the state count of a ring counter with the same number of flip-flops. They generate clean, overlap-free sequences used in ADC timing, phase generators, and FSK modulators.

Core Concept

A Johnson counter (also called a twisted-ring or switch-tail counter) feeds back the complement of the last flip-flop output to the input of the first. This single inversion doubles the number of valid states to 2N for N flip-flops, compared to N states in a plain ring counter.

The 74LS164 8-bit shift register can implement an 8-bit Johnson counter by connecting Q7_bar to the serial input. The 74HC4017 is a dedicated 5-stage Johnson counter and decade counter/divider with 10 decoded active-high outputs. It operates from 2 V to 6 V with a 15 MHz clock and 4 mW at 5 V.

Each transition in a Johnson counter changes only one bit at a time. This Gray-code-like property means no glitches appear on decoded outputs. Combinational decoding of any Johnson state requires only a 2-input AND or NAND gate, making it very efficient for state machine output logic.

Boolean Expression

The feedback equation is D0 = QN-1_bar. All other stages are D_k = Q_(k-1). The 2N states form two mirror-image halves: the first N clocks shift 1s in; the next N clocks shift 0s in.

Any state S_i can be decoded with a 2-input gate. State 0 (all zeros) needs no gate. State 1 (10...0) decodes as Q0·Q1_bar. State 2N-1 (all ones) is just AND of all Q outputs. This simplicity is why Johnson counters replace binary counters in many control applications.

Given:
Trace a 3-bit Johnson counter for all 6 states.
Initial state: Q2Q1Q0 = 000.

Formula / Rule:
D0 = Q2_bar (inverted feedback from last FF)
D1 = Q0, D2 = Q1

Step by step:
State 0: Q2Q1Q0 = 000
  D0=Q2_bar=1, D1=Q0=0, D2=Q1=0
State 1: Q2Q1Q0 = 001 (wait: D0 loads into Q0)
  Actually Q0 gets D0=1, Q1 gets D1=Q0=0, Q2 gets D2=Q1=0
  => 001? No: Q0=new D0=1, Q1=old Q0=0, Q2=old Q1=0 => 100
Let me index correctly (Q0 is leftmost/first FF):
  State 0: 000 -> D0=1 -> next Q0=1, Q1=Q0=0, Q2=Q1=0 => 100
State 1: 100 -> D0=Q2_bar=1 -> Q0=1, Q1=1, Q2=0 => 110
State 2: 110 -> D0=Q2_bar=1 -> Q0=1, Q1=1, Q2=1 => 111
State 3: 111 -> D0=Q2_bar=0 -> Q0=0, Q1=1, Q2=1 => 011
State 4: 011 -> D0=Q2_bar=0 -> Q0=0, Q1=0, Q2=1 => 001
State 5: 001 -> D0=Q2_bar=0 -> Q0=0, Q1=0, Q2=0 => 000

Final Answer:
000->100->110->111->011->001->000
6 unique states from 3 flip-flops. Period = 6 clock cycles.

Exam Tip: The most tested Johnson counter fact: N flip-flops give 2N valid states (not 2^N). A 4-bit Johnson counter has 8 states, not 16. The 74HC4017 is a 5-stage Johnson counter giving 10 states — that is why it is used as a decade counter. Also note that any adjacent state pair in a Johnson counter differs by exactly one bit, which simplifies output decoding to 2-input gates.

Key Properties

• 74HC4017: 5-stage Johnson decade counter, 10 decoded outputs, 2–6 V, 15 MHz, 4 mW
• 74LS164: 8-bit SIPO shift register, 36 MHz, can implement 8-bit Johnson counter
• N flip-flops produce 2N states — double the ring counter for same hardware
• Single-bit transitions between consecutive states — no glitches on decoded outputs
• Any state decodes with a 2-input AND/NAND gate (no complex combinational logic)
• Lockout: 2^N - 2N invalid states exist; power-up may land in invalid cycle
• Self-starting fix: feedback D0 = Q(N-1)_bar + (Q0·Q(N-1)) detects some invalid states

Quick Revision

• Johnson = twisted ring: connect Q(last)_bar to D(first)
• N flip-flops -> 2N states (ring gives only N states)
• Each state differs from adjacent by one bit only (single-bit transition)
• State decoding: 2-input AND or NAND gate per state
• 74HC4017 is the standard decade Johnson counter with 10 decoded outputs
• Invalid states: 2^N - 2N states are outside the valid cycle
• Used in phase generators, ADC timing, and LED chasers
• Exam trap: Confusing 2N states (Johnson) with N states (ring) or 2^N states (binary counter) — these three are different and each is tested separately in GATE