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Contents

Digital Electronics

Number Systems

Binary Number System Octal Number System Hexadecimal Number System Number System Conversions Binary Addition Binary Subtraction 1s Complement 2s Complement Signed Number Representation BCD Code Gray Code Excess-3 Code ASCII Code Error Detection Codes Hamming Code

Logic Gates

AND Gate OR Gate NOT Gate NAND Gate NOR Gate XOR Gate XNOR Gate Universal Gates NAND Universal Gates NOR Multi-Input Gates Buffer Gate TTL Logic Family CMOS Logic Family TTL vs CMOS Comparison Logic Level Interfacing

Boolean Algebra

Boolean Algebra Axioms Boolean Algebra Theorems De Morgan Theorem 1 De Morgan Theorem 2 De Morgan Applications Boolean Expression Simplification Canonical SOP Form Canonical POS Form Minterm and Maxterm Relationship K-Map 2 Variable K-Map 3 Variable K-Map 4 Variable K-Map Don't Care Conditions K-Map POS Simplification Quine-McCluskey Method Prime Implicant Chart

Combinational Circuits

Sequential Circuits

Memory & PLDs

ROM Architecture PROM EPROM and EEPROM SRAM DRAM SRAM vs DRAM Flash Memory PLA PAL CPLD FPGA Architecture FPGA vs ASIC

Digital System Design

Propagation Delay Setup and Hold Time Static Hazards Dynamic Hazards Glitches and Races Synchronous Design Principles Clock Skew and Jitter Asynchronous Circuit Design

Other Topics

Other Subjects

Analog Electronics Signals & Systems Control Systems Electromagnetic Theory Digital Communication Analog Communication Network Analysis Microprocessors VLSI Design Verilog HDL Power Electronics Embedded Systems DSP Electronic Devices

Section Progress56%

15 of 27 articles

Johnson Counter

Twisted ring counter, 2N states from N flip-flops.

Updated: 19 March 2026

8 min read

Johnson Counter Quiz

Test your grasp of Johnson counter state sequences and flip-flop utilization.

Question 1 of 3

Q1.A 3-bit Johnson counter starts at state 000. What is the correct state sequence for the first 4 clock pulses?

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BCD Counter

Mod-10 counter, 0000 to 1001, auto reset.

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Mod-N Counter

Arbitrary modulus counter design, feedback reset logic.

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Asynchronous Counter

Ripple counter, propagation delay accumulation.

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Synchronous Counter

Common clock, simultaneous switching, faster operation.

8 min read

Up Down Counter

Bidirectional counting, control input for direction.

4 min read

SISO Shift Register