Propagation Delay

Every timing budget in an FPGA datapath and every setup/hold calculation in a PCB design starts with propagation delay. It is the single most important timing parameter in the 74-series datasheet, and it determines the maximum clock frequency of any synchronous system.

Core Concept

Propagation delay (tpd) is the time between the 50% point of an input transition and the 50% point of the resulting output transition. Two values are defined: tpLH is the delay when the output goes Low-to-High, and tpHL is the delay when the output goes High-to-Low. These differ because PMOS pull-up networks and NMOS pull-down networks have different drive strengths.

The average propagation delay tpd = (tpLH + tpHL) / 2 is used in timing budgets. The maximum operating frequency of a combinational path is fmax = 1 / (sum of tpd along the critical path). Adding more gate stages in series increases total delay and reduces fmax.

The 74AS00 quad NAND has tpd = 1.7 ns typical at 5 V, making it one of the fastest TTL parts. The CD4011 CMOS NAND has tpd = 50 ns at 5 V. The 74HC00 sits between them at 7 ns and operates from 2 V to 6 V with near-zero static power. Fan-out of 74HC is 50 CMOS loads or 10 LS-TTL loads.

Boolean Expression

The critical path delay for a combinational circuit is T_total = Σ tpd(stage_i) for all gates i on the longest path. Maximum clock frequency is fmax = 1 / (T_total + tsetup + tskew). Each gate family has its own tpd value. Cascading gates multiplies delay. The critical path is the path with the highest total delay, not necessarily the path with the most gates.

Given:
A combinational circuit has 3 gate stages:
Stage 1: 74LS00 NAND  tpd = 9 ns
Stage 2: 74LS08 AND   tpd = 14 ns
Stage 3: 74LS32 OR    tpd = 14 ns
Flip-flop setup time = 20 ns

Formula / Rule:
T_critical = sum of tpd along critical path
fmax = 1 / (T_critical + t_setup)

Step by step:
Step 1: T_critical = 9 + 14 + 14 = 37 ns
Step 2: Total time = 37 + 20 = 57 ns
Step 3: fmax = 1 / 57 ns = 1 / (57 x 10^-9)
        fmax = 17.5 MHz

Final Answer:
Maximum clock frequency = 17.5 MHz
System cannot be clocked faster without timing violations.

Exam Tip: GATE and Anna University questions ask for fmax of a circuit given gate delays and flip-flop setup time. Always add the flip-flop setup time to the combinational delay — forgetting this is the most common mistake. Also remember tpLH and tpHL are measured between 50% points of the waveform, not 0%/100%. Do not confuse propagation delay with rise time (10%–90%) or fall time (90%–10%).

Key Properties

• 74LS family: tpd ≈ 9–14 ns, supply 5 V, fan-out 20 TTL loads
• 74HC family: tpd ≈ 7 ns at 5 V, supply 2–6 V, fan-out 50 CMOS loads
• 74AS family: tpd ≈ 1.5–2 ns, fastest TTL sub-family, supply 5 V
• CD4000 CMOS: tpd ≈ 50–100 ns at 5 V, very low power, wide supply 3–18 V
• tpLH ≠ tpHL in most gates; datasheets list both values separately
• Measured at 50% of output voltage swing into a 50 pF standard load
• Critical path determines system fmax; optimise by reducing gate count on that path

Quick Revision

• Propagation delay = time from 50% input to 50% output transition
• tpLH: output Low-to-High delay; tpHL: output High-to-Low delay
• tpd(avg) = (tpLH + tpHL) / 2
• fmax = 1 / (sum of tpd on critical path + flip-flop setup time)
• 74AS00 NAND: 1.7 ns; 74HC00 NAND: 7 ns; CD4011 NAND: 50 ns
• Cascading n identical gates multiplies delay by n
• Rise time and fall time are not the same as propagation delay
• Exam trap: forgetting to add flip-flop setup time when computing fmax from gate delays