Half Adder

The half adder is the most fundamental arithmetic circuit in digital electronics. It performs binary addition of two single-bit inputs and produces a two-bit output: the Sum bit and the Carry bit. Understanding the half adder is essential before studying full adders, parallel adders, and ALU design, all of which are important topics in GATE and university examinations.

Core Concept: Binary Addition with Two Inputs

Binary addition of two single bits follows four possible cases: 0+0=0 (sum=0, carry=0), 0+1=1 (sum=1, carry=0), 1+0=1 (sum=1, carry=0), and 1+1=10 in binary (sum=0, carry=1). The half adder circuit captures exactly these four cases using just two logic gates. It is called a half adder because it adds only two bits and produces a carry output, but cannot accept a carry input from a previous stage.

The Sum output is 1 when exactly one of the two inputs is 1. This is precisely the behavior of an XOR (exclusive OR) gate. The Carry output is 1 only when both inputs are 1 simultaneously, which matches the AND gate behavior. These two Boolean identities form the complete implementation of the half adder.

Mathematical Expression

The two output expressions of a half adder are formally derived from the truth table using Boolean algebra or K-Map simplification. For inputs A and B, the Sum output is S = A XOR B = AB' + A'B. The Carry output is C = A AND B = AB. These are minimal expressions and cannot be simplified further.

The Sum equation AB' + A'B corresponds to the K-Map cells m1 and m2 (the two diagonal 1s in a 2-variable K-Map). Since these cells are not adjacent in K-Map terms, they cannot be grouped, confirming that the XOR function is not further reducible in standard SOP form. The Carry equation AB corresponds to just m3 in the K-Map.

Practical Understanding: Gate Implementation

A half adder requires exactly one XOR gate and one AND gate. In terms of NAND gate implementation (universal gate), a half adder can be implemented using 5 NAND gates. This is because an XOR gate requires 4 NAND gates and an AND gate requires 2 NAND gates, but sharing of intermediate NAND outputs reduces the total to 5. This count is sometimes asked in GATE problems.

The half adder is the building block of ripple carry adders and parallel adders. A full adder is constructed by combining two half adders and one OR gate. Multi-bit addition is achieved by cascading full adders, with the carry output of one stage feeding as carry input to the next stage.

Solved Numerical Example

Using the half adder logic, manually compute the binary addition of A=1 and B=1, then verify using the circuit equations.

Given:
A = 1, B = 1 (single-bit binary inputs)

Why this formula applies:
Half adder computes Sum and Carry independently using XOR and AND.

Formula:
Sum (S)   = A XOR B = AB' + A'B
Carry (C) = A AND B = AB

Substitution:
S = A XOR B = 1 XOR 1
C = A AND B = 1 AND 1

Calculation:
A XOR B: A=1, B=1 → same inputs → XOR output = 0
A AND B: both 1 → AND output = 1

Result: S = 0, C = 1
Binary interpretation: 1 + 1 = 10 in binary

Verification:
Decimal check: 1 + 1 = 2 (decimal)
Binary 10 = 2 (decimal) ✓

Final Answer:
Sum = 0, Carry = 1
This represents the binary result 10, i.e., decimal 2.

Exam Tip: The half adder cannot process a carry input (Cin). For multi-bit addition, full adders are always used for intermediate bit positions. In GATE, questions often ask how many half adders and full adders are needed for an n-bit adder: the answer is one half adder for the least significant bit (LSB) stage and (n-1) full adders for the remaining bits, if the design uses half adder at the LSB.

Quick Revision

• Half adder adds two single bits and produces Sum and Carry outputs. It has no Carry input.
• Sum = A XOR B (implemented with XOR gate). Carry = A AND B (implemented with AND gate).
• Half adder requires 2 gates: 1 XOR + 1 AND. Using NAND gates only: 5 NAND gates are needed.
• Truth table has 4 rows. Carry is 1 only for the (1,1) input combination.
• Limitation: Cannot accept carry input from a previous stage. This is resolved by the Full Adder.
• GATE trap: Half adder is NOT sufficient for multi-bit binary addition at intermediate stages. Only at the LSB can a half adder be used.
• Full adder = 2 half adders + 1 OR gate.