Binary Addition

Binary addition is the fundamental arithmetic operation inside every half adder and full adder circuit. The 74LS283 4-bit binary adder IC implements this exact logic in TTL hardware.

Core Concept

Binary addition follows four simple rules: 0+0=0, 0+1=1, 1+0=1, and 1+1=10 (sum 0, carry 1). These four cases define the half adder circuit which handles two single-bit inputs with no carry-in.

The full adder extends this to three inputs: A, B, and a carry-in (Cin). It produces a Sum and a Carry-out. Full adders are cascaded to build multi-bit adders. The 74LS283 is a 4-bit binary full adder with internal carry lookahead, operating at 5V with a propagation delay of approximately 24 ns and a fan-out of 10 in TTL.

When adding multi-bit numbers, carry propagation from LSB to MSB is the critical timing path. Ripple-carry adders are simple but slow. Carry-lookahead adders like the 74S182 reduce delay by computing carry bits in parallel using generate and propagate signals.

Boolean Expression

For the full adder: Sum = A ⊕ B ⊕ Cin and Cout = AB + BCin + ACin. The Sum is a three-input XOR. The Carry-out is a majority function — it is 1 whenever two or more of the three inputs are 1.

Given:
  Add two 4-bit binary numbers: A = 1011, B = 0110

Formula / Rule:
  Column-by-column addition from LSB, propagate carry left

Step by step:
  Bit 0: 1 + 0 = 1, Carry = 0
  Bit 1: 1 + 1 = 0, Carry = 1
  Bit 2: 0 + 1 + 1(carry) = 0, Carry = 1
  Bit 3: 1 + 0 + 1(carry) = 0, Carry = 1
  Final carry out = 1 (overflow into bit 4)

    1011
  + 0110
  ------
   10001

Final Answer:
  1011 + 0110 = 10001  (decimal: 11 + 6 = 17, correct)

Exam Tip: When adding two n-bit numbers, the result can be (n+1) bits due to the final carry-out. GATE questions on overflow ask whether the result can be represented in n bits. For unsigned addition, overflow occurs if there is a carry-out from the MSB. For signed 2s complement addition, overflow occurs if the carry into the MSB differs from the carry out of the MSB.

Key Properties

• Four basic rules: 0+0=0, 0+1=1, 1+0=1, 1+1=10
• Half adder: 2 inputs, no carry-in; Sum = A XOR B, Carry = A AND B
• Full adder: 3 inputs (A, B, Cin); Sum = A XOR B XOR Cin
• 74LS283 4-bit adder: tpd = 24 ns, Vcc = 5V, TTL family, fan-out = 10
• Ripple-carry adder delay grows linearly with bit width; carry lookahead reduces it to O(log n)
• Carry generate G = AB; carry propagate P = A XOR B; used in lookahead logic
• Multi-bit addition is the core operation in the arithmetic logic unit (ALU) of every CPU

Quick Revision

• Binary addition: 1+1 = 10 (sum 0, carry 1)
• Half adder: Sum = A⊕B, Carry = AB
• Full adder: Sum = A⊕B⊕Cin, Cout = AB + BCin + ACin
• 74LS283: 4-bit full adder IC, 24 ns propagation delay
• Cascade full adders to handle wider operands
• Carry-lookahead reduces critical path delay in wide adders
• Final carry-out from an n-bit adder indicates result needs n+1 bits
• Exam trap: confusing unsigned overflow (carry-out from MSB) with signed overflow (carry-in XOR carry-out at MSB)