Mod-N Counter

A mod-N counter counts through exactly N states and then wraps back to zero. Baud rate generators, clock dividers in UART circuits, and PWM period counters all rely on mod-N designs with N not a power of two.

Core Concept

A mod-N counter divides the input clock by exactly N. It uses a binary counter plus reset logic that forces the counter to 0000 after reaching count N. The number of flip-flops required is the ceiling of log base 2 of N.

The 74LS163 is the standard IC for mod-N counters. Its synchronous load pin allows preset to any value, making it easy to start from a non-zero count. The 74HC163 is the CMOS equivalent, operating from 2 V to 6 V. Both have four flip-flops, supporting mod-2 through mod-16 directly.

Two methods exist for building mod-N counters. The reset method lets the counter reach N and then resets to 0. The preset method loads a starting value of 2^k minus N and counts up to 2^k, creating N clock periods per cycle. The preset method uses synchronous load and avoids glitches entirely.

Boolean Expression

For the reset method, CLR = AND of all bits that are 1 in the binary representation of N. For mod-6 (N=6=110), CLR = Q2·Q1. For mod-10 (N=10=1010), CLR = Q3·Q1.

For the preset method, load value = 2^k - N where k is the number of flip-flops. For mod-6 with k=3, load = 8-6 = 2 (010). The counter counts 2,3,4,5,6,7 then rolls over to 0 — but wait, that is 6 states only if k=3 and 7 triggers a carry back to the loaded 2. So use the RCO (terminal count) as the load signal.

Given:
Design a mod-12 counter using 74LS163 (4-bit synchronous counter).
Method: Preset (load) method to avoid output glitches.

Formula / Rule:
k = ceil(log2(12)) = 4 flip-flops
Load value = 2^4 - 12 = 16 - 12 = 4 (binary 0100)
Counter counts 4,5,6,7,8,9,10,11,12,13,14,15 -> load 4 again
Wait: that is 12 states only from 4 to 15 inclusive.
Actually 15-4+1 = 12 states. Correct.

Step by step:
Set DCBA parallel inputs = 0100 (load value)
Connect RCO (pin 15) to active-low LOAD_bar pin (pin 9)
Connect ENP and ENT high (enable counting)
  When count reaches 15 (1111), RCO goes HIGH
  RCO asserted -> LOAD_bar goes LOW at next clock edge
  Counter loads 0100 (4) synchronously
  No glitch, no spurious state

State sequence: 4->5->6->7->8->9->10->11->12->13->14->15->4
Period = 12 clock cycles

Final Answer:
Load value = 0100, connect RCO to LOAD_bar.
Mod-12 achieved with one 74LS163 and no external gates.

Exam Tip: GATE problems frequently ask you to count the number of flip-flops for a given mod-N. Use ceil(log2(N)) — for mod-5, that is 3; for mod-9, that is 4. A second common trap is confusing the reset method (momentary invalid state possible with async clear) with the preset method (clean, glitch-free). Always specify which method you use in design questions.

Key Properties

• 74LS163: synchronous clear and load, 4 bits, 25 MHz max clock, 93 mW, 5 V
• Number of flip-flops for mod-N: ceil(log2(N)) — minimum required
• Reset method: detect state N with AND gate, issue CLR — may glitch with async clear
• Preset method: load (2^k - N), count to 2^k - 1, use RCO to trigger reload
• Preset method is glitch-free; preferred in noise-sensitive designs
• 74LS163 RCO goes high only at state 15 with ENP=ENT=1; gate ENT carefully
• Two 74LS163s cascaded with first RCO into second ENT gives mod-2 to mod-256

Quick Revision

• Mod-N counter divides clock by N and cycles through N states
• Flip-flops needed: ceil(log2(N)); e.g. mod-6 needs 3, mod-10 needs 4
• Reset method: CLR = AND of bits that are 1 in binary(N)
• Preset method: load = 2^k - N; count to 2^k - 1, use RCO to reload
• 74LS163 synchronous clear guarantees no glitch even with reset method
• RCO pin of 74LS163 is high only at terminal count (1111) when both enables are high
• Cascade two 74LS163s for mod-N where N > 16
• Exam trap: Calculating load value as N instead of 2^k - N — this gives the wrong count length