Synchronous Design Principles

Every modern CPU and FPGA runs on a single clock edge — miss it and the whole pipeline stalls. Synchronous design is the discipline that makes billions of gates agree on timing without chaos.

Core Concept

In a synchronous circuit, every state change happens on a specific clock edge — typically the rising edge. No flip-flop updates between edges. This makes timing analysis tractable because you only need to verify one interval: the clock period.

The 74HC74 dual D flip-flop is a classic synchronous element. It samples its D input on the rising clock edge and holds Q stable until the next edge. Propagation delay from clock to Q is 7 ns at 5 V, fan-out is 10 TTL loads, and supply voltage ranges from 2 V to 6 V.

The critical path is the longest combinational delay between any two flip-flop stages. It must fit inside one clock period minus setup time. Violating this causes metastability — the flip-flop output oscillates unpredictably until it resolves, sometimes to the wrong value.

Boolean Expression

The timing constraint for a synchronous stage is: t_pd + t_setup ≤ T_clk. Here t_pd is the combinational propagation delay, t_setup is the flip-flop setup time, and T_clk is the clock period. The maximum operating frequency is f_max = 1 / (t_pd + t_setup + t_skew).

Given:
  FF setup time (tsetup) = 3 ns
  FF propagation delay (tpd_ff) = 7 ns
  Combinational logic delay (tpd_combo) = 15 ns
  Clock skew (tskew) = 1 ns

Formula / Rule:
  T_clk(min) = tpd_ff + tpd_combo + tsetup + tskew

Step by step:
  T_clk(min) = 7 + 15 + 3 + 1
             = 26 ns
  f_max      = 1 / 26 ns
             = 38.46 MHz

  Hold time check:
  tpd_ff > thold + tskew
  7 ns > 2 ns + 1 ns = 3 ns  --> PASS

Final Answer:
  Minimum clock period = 26 ns
  Maximum clock frequency = 38.46 MHz
  Hold time check passes

Exam Tip: GATE frequently asks you to find f_max from a pipeline diagram. Always add clock skew to the critical path — many students forget it. Also remember that hold time violations are clock-frequency independent; they cannot be fixed by slowing the clock, only by adding buffer delay on the data path.

Key Properties

• 74HC74 propagation delay (clock to Q): 7 ns at 5 V, 14 ns at 2 V
• Setup time for 74HC74: 3 ns minimum; hold time: 1 ns minimum
• Fan-out: 10 LSTTL loads; power dissipation: 80 µW static (CMOS)
• Supply voltage: 2 V to 6 V (74HC series); TTL-compatible inputs at 5 V
• Clock-to-Q delay determines the earliest time next-stage data is valid
• Synchronous reset clears flip-flop only on the clock edge, not asynchronously
• All state changes occur at one global clock edge, making formal verification tractable

Quick Revision

• Synchronous circuits change state only on a clock edge
• Critical path = longest combinational delay between two flip-flops
• f_max = 1 / (t_pd_ff + t_pd_combo + t_setup + t_skew)
• Hold time violation cannot be fixed by reducing clock frequency
• 74HC74: 7 ns clock-to-Q, 3 ns setup, 1 ns hold at 5 V
• Metastability occurs when setup or hold time is violated
• Synchronous reset requires a clock edge; asynchronous reset does not
• Exam trap: forgetting to add clock skew when calculating f_max — skew reduces the available timing budget