PLA

When Altera built its first programmable logic chips in the 1980s, the PLA — Programmable Logic Array — was already the benchmark for implementing arbitrary Boolean functions in a single IC without custom silicon.

Core Concept

A PLA implements Sum of Products (SOP) logic using two programmable planes. The AND plane generates any desired product term (minterm or implicant) from the input variables and their complements. The OR plane then sums any subset of those product terms to form each output. Both planes are programmable, giving maximum flexibility.

The Signetics 82S100 was a classic bipolar PLA with 16 inputs, 8 outputs, and 48 product terms. It runs at 5 V TTL levels with a propagation delay of 35 ns. Fusible-link technology made it field-programmable but one-time-programmable (OTP). CMOS variants like the 82S105 offer lower power.

Because both planes are programmable, a PLA can share product terms across multiple outputs. A 4-variable function needing 6 product terms might share two of them with another output, using fewer AND gates than two independent circuits. This sharing is the PLA's key advantage over a PAL.

Boolean Expression

Any output of a PLA takes the form F = P1 + P2 + ... + Pk where each Pi is a minterm or prime implicant of the input variables. The canonical minterm form F = Σm(minterms) maps directly to the PLA: each minterm is one row of the AND plane, and the OR plane selects which minterms feed each output. In practice, a minimized SOP (Karnaugh map result) is programmed to reduce the number of product term rows needed.

Given:
  F1(A,B,C) = Σm(1,2,5,6)   -- output 1
  F2(A,B,C) = Σm(0,3,5,6)   -- output 2
  Minimize and map to PLA product terms

Formula / Rule:
  Minimize each SOP using K-map; share product terms if possible

Step by step:
  F1 K-map: group (1,5)=A'C, (2,6)=A C', (5,6)?no -- try: (1,5)=B'C, (2,6)=BC'
  F1 = B'C + BC' = B XOR C  -- 2 product terms
  F2 K-map: group (0,2)? ... simplify to A'B'+AB, A'BC'
  F2 = A'B' + AB + A'BC'  -- or share terms where possible

  PLA AND plane rows (product terms):
    P1 = B'C
    P2 = BC'
    P3 = A'B'
    P4 = AB
    P5 = A'BC'

  PLA OR plane connections:
    F1 = P1 + P2
    F2 = P3 + P4 + P5

Final Answer:
  5 product terms implement both outputs.
  Without sharing, two separate circuits would need 5+3=8 AND gates.

Exam Tip: In GATE questions on PLA vs PAL, the key difference is: PLA has both AND and OR planes programmable; PAL has only the AND plane programmable (OR plane is fixed). Because PAL's OR plane is fixed, product terms cannot be shared between outputs. PLA is more flexible but more complex to program. Also remember: a PLA can implement any SOP after minimization; it does NOT require minterms — it uses prime implicants.

Key Properties

• Both AND plane and OR plane are user-programmable — maximum flexibility for SOP logic
• Signetics 82S100: 16 inputs, 8 outputs, 48 product terms, 35 ns propagation delay, 5 V TTL
• Product term sharing: one AND-plane row can feed multiple OR-plane outputs, saving area
• One-time-programmable (OTP) with bipolar fuses; CMOS EEPROM-based PLAs are reprogrammable
• Fan-out: typically 10 TTL loads; CMOS variants drive >50 CMOS inputs
• Power dissipation: bipolar 82S100 ~525 mW; CMOS equivalents drop to ~5-20 mW
• Replaced in practice by PAL then CPLD, but still appears in GATE syllabi as the foundational PLD concept

Quick Revision

• PLA = Programmable Logic Array = programmable AND plane + programmable OR plane
• Implements SOP (Sum of Products) expressions; OR gate inputs are selectable per output
• Both planes programmable → product terms shareable across outputs
• Classic IC: 82S100 (Signetics), 16×48×8 (inputs × product terms × outputs)
• Programming: fuse blown = disconnect; fuse intact = connect (bipolar OTP devices)
• Minimization step: always minimize SOP (K-map) before programming to reduce AND-plane rows
• Exam trap: students say 'PLA implements POS' — PLA directly implements SOP; POS requires additional inversion