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Synchronous Counter

Common clock, simultaneous switching, faster operation.

Mohith N

Updated: 7 April 2026

8 min read

Synchronous counters drive everything from CPU program counters to frequency dividers in PLLs. Unlike ripple counters, every flip-flop in a synchronous counter clocks at the same instant, eliminating glitches that corrupt downstream decoders.

Figure 1: Synchronous counter structure using T flip-flops; all clock inputs tied together

Core Concept

A synchronous counter connects the clock signal simultaneously to all flip-flops. State transitions happen on the same clock edge. There are no cumulative propagation delays between stages, unlike asynchronous (ripple) counters.

The 74LS163 is a 4-bit synchronous binary counter with synchronous clear and load. Its maximum clock frequency is 25 MHz. Propagation delay from clock to output is 24 ns typical. The 74HC163 runs at 3.3 V or 5 V with a 50 MHz clock limit and under 1 mW static power.

Input equations for T flip-flop implementation follow a simple carry pattern. T0 = 1 always. T1 = Q0. T2 = Q0·Q1. T3 = Q0·Q1·Q2. Each stage toggles only when all lower bits are 1, which is the binary carry condition.

Boolean Expression

For an n-bit synchronous up counter using T flip-flops, the input equation for stage k is T_k = Q0 · Q1 · Q2 · ... · Q(k-1). This is the AND of all lower-order outputs. For a JK implementation, J_k = K_k = T_k.

The carry out (RCO) of the 74LS163 is Q3·Q2·Q1·Q0·ENP·ENT, going high only at count 15. This RCO signal cascades to the ENT pin of the next 74LS163 to build 8-bit or wider counters.

Example

Given:
Trace a 4-bit synchronous up counter from state 0110 (decimal 6).

Formula / Rule:
T0=1, T1=Q0, T2=Q0.Q1, T3=Q0.Q1.Q2
FF toggles when T=1 at clock edge.

Step by step:
State 0110: Q3=0, Q2=1, Q1=1, Q0=0
  T0=1 => Q0 toggles: 0->1
  T1=Q0=0 => Q1 no change: stays 1
  T2=Q0.Q1=0.1=0 => Q2 no change: stays 1
  T3=Q0.Q1.Q2=0 => Q3 no change: stays 0
Next state: 0111 (decimal 7)

State 0111: Q3=0, Q2=1, Q1=1, Q0=1
  T0=1 => Q0 toggles: 1->0
  T1=Q0=1 => Q1 toggles: 1->0
  T2=Q0.Q1=1.1=1 => Q2 toggles: 1->0
  T3=Q0.Q1.Q2=1.1.1=1 => Q3 toggles: 0->1
Next state: 1000 (decimal 8)

Final Answer:
0110 -> 0111 -> 1000 (counts 6, 7, 8 correctly)

Exam Tip: GATE frequently asks for the number of logic gates needed to implement a synchronous counter. Count the AND gates for the T-input carry chain: 0 gates for T0, 1 two-input AND for T1, and so on. A 4-bit counter needs 0+1+1+1 = 3 AND gates plus 4 T flip-flops. For JK implementation, connect J=K=T for each stage. Never confuse this with an asynchronous counter where each clock input connects to the previous Q output.

Key Properties

74LS163: max clock 25 MHz, propagation delay 24 ns, supply 5 V, power 93 mW
74HC163: max clock 50 MHz, supply 2–6 V, power under 1 mW static (CMOS)
Synchronous clear and synchronous load on 74LS163 prevent glitches during reset
RCO (ripple carry out) pin enables easy cascading of multiple 163s
T-FF input for stage k: AND of all Q outputs of stages 0 through k-1
Maximum frequency limited only by flip-flop clock-to-Q delay plus AND gate delay
Fan-out of 74LS163 outputs: 20 LS TTL loads per output pin

Quick Revision

All flip-flops share the same clock line — that is the defining feature
T0 = 1, T1 = Q0, T2 = Q0Q1, T3 = Q0Q1Q2 for a 4-bit up counter
JK implementation: J = K = T for every stage
74LS163 has synchronous clear; 74LS161 has asynchronous clear — know the difference
RCO of first 163 connects to ENT of second 163 for cascading
Maximum clock frequency is NOT divided by n for a synchronous counter
For a down counter, replace Q with Q-bar in all T-input AND expressions
Exam trap: Claiming a synchronous counter has cumulative propagation delay — it does not; only the AND-gate carry chain adds a small fixed delay