SRAM

SRAM is the memory inside every CPU cache — L1, L2, and L3. Its speed directly determines how fast a processor can execute code. Without SRAM caches, modern GHz processors would spend most of their time waiting for DRAM.

Core Concept

Static RAM (SRAM) stores each bit using a pair of cross-coupled inverters — a bistable latch. The standard cell uses 6 transistors (6T): two PMOS pull-up transistors (M1, M2), two NMOS inverter transistors (M3, M4), and two NMOS access transistors (M5, M6). The cross-coupled pair (M1-M3 and M2-M4) form two inverters whose outputs feed each other's inputs, creating stable 0 and 1 states. No capacitor is involved, so no periodic refresh is needed.

The 6116 is a classic 2K×8 SRAM in a 28-pin DIP package. It has 11 address lines (A0–A10), 8 data lines (I/O0–I/O7), and control pins CE (chip enable), OE (output enable), and WE (write enable). Access time is 120 ns (standard) or as fast as 45 ns (6116-45). The 62256 is the 32K×8 variant with 15 address lines. Modern high-speed SRAMs like the CY7C1021 achieve access times below 10 ns and are used as CPU cache memory.

Reading: the wordline selects a row, enabling M5 and M6. The stored Q value drives the bitline BL through M5, and Q-bar drives BL-bar through M6. A differential sense amplifier detects the small voltage difference between BL and BL-bar and amplifies it to full logic levels. Writing: the data to be written is driven onto BL and BL-bar before the wordline is asserted, overriding the stored state and flipping the latch.

Boolean Expression

The SRAM cell is a SR latch implemented with CMOS inverters. The characteristic equation is Q(next) = Q(current) when the wordline is deasserted (hold state), and Q(next) = D when the wordline is asserted during a write cycle, where D is the data driven onto the bitline. For the array: address lines A[n-1:0] select one of 2ⁿ rows; a column decoder selects the specific byte within the row when the word width is greater than the basic cell width.

Given:
SRAM 6116: 2K × 8, access time 120 ns
Calculate: total cells, address lines needed, data bus width

Formula / Rule:
Total bits = words × bits-per-word
Address lines n: 2^n = number of words

Step by step:
Words = 2K = 2 × 1024 = 2048
Bits per word = 8
Total bits = 2048 × 8 = 16,384 bits = 16 Kbits

Address lines: 2^n = 2048 → n = 11 (A0 through A10)
Data lines: 8 (D0 through D7, bidirectional I/O)

Read cycle timing:
t_ACS (address to chip select): address stable before CE↓
t_ACC (access time) = 120 ns: output valid after address stable
t_OE: output enable to valid data ≈ 50 ns

Write cycle:
WE↓ latches address and data onto selected cell
Write pulse width ≥ 70 ns for reliable latch flip

Final Answer:
6116 SRAM: 11 address lines, 8 data lines, 16 Kbits total
Read latency = 120 ns (no refresh wait, unlike DRAM)

Exam Tip: The key SRAM vs DRAM distinction for GATE is: SRAM uses a bistable latch (no refresh), DRAM uses a capacitor (needs refresh every ~64 ms). SRAM is faster (sub-10 ns vs 50+ ns), uses more transistors per cell (6T vs 1T+1C), and is more expensive per bit. SRAM is used for cache; DRAM for main memory. Another trap: SRAM is volatile (loses data when power is removed) — do not confuse with non-volatile ROM just because it has no refresh.

Key Properties

• Cell structure: 6 transistors (2 PMOS + 4 NMOS) — no capacitor, no refresh required
• 6116: 2K×8, 11 address lines, 28-pin DIP, tACC = 45–120 ns, VCC = 5V, CMOS or TTL compatible
• 62256: 32K×8, 15 address lines, tACC = 55–150 ns — standard SRAM in Z80 and 6502 systems
• Modern cache SRAM: CY7C1021 (64K×16), tACC < 10 ns, 3.3V supply
• Power: standby current 20–100 µA (CMOS SRAM); active ~20 mA at full speed
• Volatile: data lost without power — unlike ROM/Flash but unlike DRAM, no periodic refresh needed
• Cell area: ~50–100 F² per bit (larger than DRAM 1T cell at ~6 F²) — limits density

Quick Revision

• SRAM stores bits in cross-coupled inverter pair (SR latch) — 6 transistors per cell
• No capacitor → no charge leakage → no refresh needed (unlike DRAM)
• Read: wordline enables access transistors → sense amp detects BL vs BL-bar difference
• Write: drive BL/BL-bar before asserting WL → flips the latch to new state
• 6116 = 2K×8 SRAM, 11 address lines, tACC = 120 ns — classic textbook device
• SRAM is faster and lower latency than DRAM; used for CPU caches (L1/L2/L3)
• SRAM is volatile — power loss erases data, just like DRAM
• Exam trap: thinking SRAM does not need refresh means it is non-volatile — it is still volatile, refresh and non-volatility are separate concepts