Asynchronous Circuit Design

USB arbitration, DRAM row access, and CPU cache coherence all use circuits that respond to events, not clock edges. Asynchronous design removes the global clock constraint entirely.

Core Concept

An asynchronous circuit has no global clock. Logic transitions happen in response to input changes. Modules communicate through handshake protocols: the sender drives a REQ signal, the receiver responds with ACK. No timing assumptions about propagation delay are needed — correctness depends only on signal ordering.

The central hazard in asynchronous logic is a glitch — a spurious output pulse caused by unequal path delays through combinational logic. A static-1 hazard produces a momentary 0 when the output should remain 1. Glitches can latch incorrect values into storage elements. Designers use hazard-free cover in Karnaugh maps to eliminate them.

The Muller C-element (completion element) is the key building block. Its output goes high only when all inputs are high, and low only when all inputs are low. It holds its state otherwise. Built from 74LS00 NAND gates, it acts as the handshake arbiter with propagation delay under 10 ns at 5 V.

Boolean Expression

The C-element characteristic equation is: Q_next = A·B + Q·(A + B). When A=B=1, Q goes high. When A=B=0, Q goes low. When A≠B, Q holds its previous value. This is the fundamental memory behavior needed for asynchronous handshake completion detection.

Given:
  Asynchronous SR latch with NOR gates
  Inputs: S (Set), R (Reset)
  Truth table to trace

Formula / Rule:
  Q = S + R'*Q_prev  (characteristic equation)
  Invalid state: S=1, R=1

Step by step:
  State 1: S=1, R=0
    Q = 1 + 0*Q_prev = 1  --> Q=1, Q_bar=0 (SET)
  State 2: S=0, R=0
    Q = 0 + 1*1 = 1      --> Q=1 (HOLD)
  State 3: S=0, R=1
    Q = 0 + 0*1 = 0      --> Q=0, Q_bar=1 (RESET)
  State 4: S=0, R=0
    Q = 0 + 1*0 = 0      --> Q=0 (HOLD)

Final Answer:
  Sequence: SET --> HOLD(1) --> RESET --> HOLD(0)
  The latch retains its last state when S=R=0
  S=R=1 is forbidden (both outputs go low = invalid)

Exam Tip: In asynchronous circuits, the forbidden state for a NOR SR latch is S=1, R=1 (both outputs become 0 — invalid). For a NAND SR latch, the forbidden state is S=0, R=0 (both outputs become 1 — invalid). These are opposite, and GATE frequently tests this distinction. Also: hazard-free logic requires adding redundant cover terms to the Karnaugh map, even if those terms are logically unnecessary.

Key Properties

• No global clock: transitions triggered by input events, not clock edges
• Handshake protocols: 2-phase (return-to-zero) or 4-phase (RTZ) with REQ/ACK
• Muller C-element built from 74LS00: propagation delay ~10 ns at 5 V
• Static-1 hazard: glitch to 0 when output should stay 1; cured by adding consensus term
• Static-0 hazard: glitch to 1 when output should stay 0; cured in POS form
• NOR SR latch forbidden state: S=R=1; NAND SR latch forbidden: S=R=0
• Advantage over synchronous: no clock distribution, lower average power, no setup/hold constraints

Quick Revision

• Asynchronous circuits have no global clock
• 4-phase handshake: REQ high, ACK high, REQ low, ACK low
• C-element holds state when inputs differ; changes only when all inputs agree
• Static-1 hazard: add consensus (redundant) term in SOP expression
• Static-0 hazard: add redundant maxterm in POS expression
• NOR SR forbidden: S=R=1; NAND SR forbidden: S=R=0
• Asynchronous design eliminates clock skew problems but requires careful hazard analysis
• Exam trap: confusing NOR latch and NAND latch forbidden states — they are exactly opposite