Verilog HDL
45 articles • Complete guide
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Curriculum
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Basics
Data types, operators, modules, testbenches
Introduction to HDLs
Verilog vs VHDL, simulation vs synthesis.
Verilog Module Structure
Module, ports, endmodule, instance hierarchy.
Data Types and Logic Values
Net (wire), Register (reg), 4-value logic (0,1,x,z).
Vectors and Arrays
Declaring buses, memories, reg [7:0] mem [0:255].
Lexical Conventions
Keywords, identifiers, numbers, whiteboard.
Verilog Operators
Arithmetic, logical, bitwise, reduction, shift, concatenation.
Port Connection Rules
Input, Output, Inout, reg/wire connection rules.
Behavioral Modeling
Always blocks, if-else, case, loops
Procedural Blocks
Always block, initial block, sensitivity lists.
Blocking vs Non-Blocking
Operators = vs <=, scheduling semantics.
Control Statements
If-else, case, casez, casex statements.
Loops in Verilog
For, while, repeat, forever loops.
FSM Behavioral Modeling
Mealy vs Moore coding styles.
Timing Controls
Delay control #, event control @, wait statement.
Block Statements
Begin-end, fork-join parallel blocks.
Task and Function
Subroutines, differences, automatic re-entrancy.
Dataflow Modeling
Continuous assignments, operators
Structural Modeling
Gate level, module instantiation, hierarchies
Gate Level Modeling
Built-in primitives (and, or, not), gate delays.
gate delays
Rise, fall, turn-off delays, min/typ/max.
Module Instantiation
Port mapping by order, by name.
Switch Level Modeling
NMOS, PMOS, CMOS switches, transmission gates.
User Defined Primitives
Creating custom combinational/sequential primitives.
Generate Blocks
Conditional and loop generate for scalable structures.
Sequential Circuits
Flip-flops, counters, state machines
Modeling Flip-Flops
D-FF, T-FF, JK-FF with async/sync resets.
Modeling Latches
Level sensitive behavior, inferring latches accident.
Modeling Counters
Up/down counter, mod-N counter.
Modeling Shift Registers
SISO, SIPO, PISO, PIPO.
Synchronous Memories
Modeling RAM/ROM with clock.
Combinational Circuits
Adders, multiplexers, encoders in Verilog
Modeling Multiplexers
Using if-else, case, assign statements.
Modeling Decoders/Encoders
Behavioral modeling of 3:8 decoder, priority encoder.
Modeling ALUs
Arithmetic Logic Unit implementation.
Modeling Adders
Half, Full, Ripple Carry Adder.
Modeling Comparators
Comparing vectors.
Verification
Testbenches, assertions, coverage
Testbench Basics
Stimulus, monitoring, checking results.
System Tasks
File I/O ($fopen), printing ($display, $monitor).
Simulation Time
Timescale directive, $time, $finish, $stop.
Randomization
Using $random for test vectors.
Assertions
Introduction to SystemVerilog Assertions (SVA).
Verification Plan
Directed vs Random testing strategies.