User Defined Primitives

Verilog provides built-in gate primitives like and, or, and nand, but complex custom logic often cannot be described efficiently using only these gates. User-Defined Primitives (UDPs) allow designers to define their own truth-table based primitives for both combinational and sequential logic. UDPs are single-output hardware descriptions that simulate faster than equivalent behavioral code and are used extensively in cell library modeling.

Core Concept Explanation

A UDP is declared using the primitive keyword instead of module. Unlike modules, UDPs have exactly one output, which must be listed first in the port list. The output can be a regular wire type for combinational UDPs, but must be declared as reg for sequential UDPs because the primitive must maintain internal state between simulation time steps.

Combinational UDPs use a truth table enclosed between table and endtable keywords. Each row of the table specifies input values and the resulting output. The wildcard symbol ? represents any logic value (0, 1, or x). Rows are matched top-to-bottom during simulation, and the first matching row determines the output. If no row matches, the output is set to x.

Sequential UDPs add a current state column between the inputs and the next-state output column, separated by colons. The table format becomes: inputs : current_state : next_state. This allows level-sensitive latches and edge-triggered flip-flops to be described. Edge transitions in inputs are written as (01) for rising edge and (10) for falling edge.

Sequential UDPs can optionally include an initial block to set the starting state of the reg output. This is only valid inside UDPs, not in regular modules, and applies only to simulation. The special symbol - in the next-state column means the output does not change, which is important for describing flip-flop behavior on non-triggering clock edges or input glitches.

Mathematical Expression

UDPs do not have an explicit formula, but the completeness of the truth table is important for simulation correctness. A combinational UDP with N inputs needs at most 3^N rows (since each input can be 0, 1, or x). In practice, wildcards like ? reduce the number of explicit rows needed. An incomplete table (where some input combinations have no matching row) causes the simulator to output x for those combinations.

For a sequential UDP modeling an edge-triggered D flip-flop, the key insight is that only rising-edge entries (01) and falling-edge entries (10) on the clock input cause state transitions. All other clock transitions (x or ?) should produce a - (no change) or explicitly drive x for safe simulation.

Practical Understanding

UDPs are the standard format used to model standard cell behavior in gate-level netlists from technology vendors. An AND2, OAI21, or DFF cell provided in a standard cell library is often internally modeled as a UDP in Verilog for efficient simulation. This is why understanding UDP syntax helps in reading and verifying library cell models during back-end verification.

One important restriction is that UDPs cannot contain structural instantiation of other modules or primitives inside them. They are purely table-driven. Also, UDPs cannot have bidirectional (inout) ports. These constraints enforce simplicity and make UDP simulation extremely fast, which is why simulation performance improves when cell models use UDPs instead of behavioral if-else code.

Given:
A 2-input combinational UDP for XOR using truth table.
Inputs: a, b. Output: out.

Why this formula applies:
XOR output is 1 when inputs differ, 0 when they are equal.
Truth table covers all input combinations explicitly.

Formula:
primitive xor_udp(out, a, b);
output out;
input a, b;
table
  0  0  :  0
  0  1  :  1
  1  0  :  1
  1  1  :  0
endtable
endprimitive

Substitution:
For a=1, b=0: match row (1  0 : 1), output = 1
For a=1, b=1: match row (1  1 : 0), output = 0

Calculation:
Simulator scans table top to bottom, first match used.

Final Answer:
out = a XOR b. Complete table ensures no x output for valid inputs.

Exam Tip: UDP output is always a single bit and always listed first in the port declaration. Sequential UDPs require output to be declared as reg. A missing row in a combinational UDP table for a particular input combination causes the output to be x for that combination, which is a simulation hazard. GATE may test whether a given UDP table is complete or identify what output results from a specific input sequence.

UDP Key Points

• UDPs use the primitive keyword instead of module and allow exactly one output port, declared first.
• Combinational UDP: table rows are input_values : output. Symbol ? means 0, 1, or x.
• Sequential UDP: table rows are input_values : current_state : next_state. Output must be reg.
• Edge notation: (01) = rising edge, (10) = falling edge, (0x) = 0 to unknown transition.
• Symbol - in next-state means no change; prevents unnecessary transitions in simulation.
• No row match for a given input combination results in output x during simulation.
• UDPs cannot instantiate other modules inside them; they are purely truth-table based.

Quick Revision

• primitive keyword declares a UDP; endprimitive closes it; one output only, listed first.
• Combinational: output reg NOT needed; table format: inputs : output.
• Sequential: output must be reg; table format: inputs : current_q : next_q.
• Wildcard symbols: ? (any), - (no change), b (0 or 1), * (any transition on that input).
• Incomplete table yields x output; always ensure all critical input combinations are covered.
• Used in standard cell library models for fast gate-level simulation.
• GATE trap: confusing combinational and sequential UDP table formats, or forgetting reg on sequential output.