Lexical Conventions

Before writing any Verilog code, a designer must understand the rules that govern how text is interpreted by the compiler and simulator. Lexical conventions define what constitutes a valid keyword, identifier, number, string, and comment, and these rules directly affect how Verilog tools parse and process source files.

Lexical rules are foundational knowledge that prevents syntax errors in everyday coding. For GATE aspirants, questions on number representation, escape sequences, and identifier rules appear in HDL theory questions and require precise understanding of the Verilog specification.

Core Concept: Keywords and Identifiers

Verilog keywords are reserved words that have predefined meaning in the language. Examples include module, wire, reg, always, assign. All Verilog keywords are lowercase. Using a keyword as an identifier is a syntax error. The language has approximately 103 reserved keywords in the IEEE 1364-2001 standard.

An identifier is a user-defined name for a module, signal, instance, parameter, or task. Valid identifiers must begin with a letter (a-z, A-Z) or an underscore (_). They can contain letters, digits (0-9), underscore, and the dollar sign ($). Identifiers cannot begin with a digit or a $. Verilog is case-sensitive, meaning clk, CLK, and Clk are three completely different identifiers. This is a common source of bugs for beginners.

An escaped identifier allows any printable ASCII character to be used in a name by preceding the entire identifier with a backslash and terminating it with a whitespace character. For example, \reset+n (with a trailing space) is a valid escaped identifier. These are rarely used in practice but may appear in synthesized netlists generated by EDA tools.

Number Literals and Base Notation

Verilog numbers follow a specific sized number format: size'base value. The size is the number of bits, the base character specifies the number system, and value is the numeric digits. Valid base characters are b or B (binary), o or O (octal), d or D (decimal), and h or H (hexadecimal). For example, 8'b1010_1111 is an 8-bit binary number where underscore is used as a readability separator and has no numerical significance.

If the size is omitted, the number is treated as a 32-bit value by default in most simulators. If the specified size is smaller than the value requires, the upper bits are truncated. If larger, the number is zero-extended. For signed numbers, the signed keyword is added before the base: 8'sb1111_0000 represents a signed 8-bit binary number.

Comments and Whitespace

Verilog supports two comment styles. A single-line comment begins with // and extends to the end of the line. A block comment begins with /* and ends with */ and can span multiple lines. Block comments cannot be nested. Whitespace (spaces, tabs, newlines) is ignored except inside string literals. Verilog is a free-format language, so statements can span multiple lines.

Mathematical Expression: Number Conversion

Converting a Verilog number literal to its decimal value follows standard positional notation. For a binary number with digits b(n-1) down to b(0), the decimal value is the sum of b(i) x 2^i for all bit positions i. For hexadecimal, each digit represents 4 bits, so 8'hAF = A(1010) in upper nibble, F(1111) in lower nibble = 10 x 16 + 15 = 175 in decimal. Understanding this conversion is essential for writing and verifying testbench stimulus values.

Solved Numerical Example

Convert the Verilog number literal 12'hA3F to its binary and decimal equivalents. Then verify that the 12-bit size specification is consistent with the value.

Given:
Verilog literal = 12'hA3F
Size = 12 bits
Base = h (hexadecimal)
Value = A3F

Why this formula applies:
Each hex digit = 4 bits. Total digits = 3. Total bits = 3 x 4 = 12.
Decimal = sum of (digit x 16^position)

Formula:
Decimal = d2 x 16^2 + d1 x 16^1 + d0 x 16^0

Substitution:
A = 10, 3 = 3, F = 15
Decimal = 10 x 256 + 3 x 16 + 15 x 1

Calculation:
= 2560 + 48 + 15 = 2623
Binary: A=1010, 3=0011, F=1111
Binary = 1010_0011_1111

Final Answer:
12'hA3F = 12'b1010_0011_1111 = 2623 in decimal.
Size check: 12 bits required for A3F. Consistent.

Exam Tip: Verilog is case-sensitive for identifiers but NOT for base specifiers. 8'hFF and 8'HFF are identical. A common GATE trap is asking whether clk and CLK are the same: they are NOT. Another trap is that keywords like module and MODULE are different, and MODULE is a valid identifier (unusual but valid).

Practical Implication

Correct use of number literals prevents simulation bugs caused by implicit size extension or truncation. Always specifying the size explicitly (for example 8'hFF instead of 255) makes the intent clear to both the tool and other engineers reading the code. Using underscore separators in long binary constants such as 32'hDEAD_BEEF greatly improves readability in testbench and constant parameter declarations.

• Sized number format is size'base value. Size gives bit width, base sets the number system, value contains the digits.
• Decimal base (d) does not support x or z values. Binary (b), octal (o), and hex (h) support x (unknown) and z (high-impedance) digits.
• Underscore _ can be placed anywhere in the value field for readability. It carries no numeric significance.
• If size is smaller than the value requires, upper bits are silently truncated. If larger, the value is zero-padded. Both can cause simulation bugs.
• Identifiers are case-sensitive. Keywords are always lowercase. Using an uppercase version of a keyword like WIRE is technically a valid identifier, not a keyword.

Quick Revision

• Verilog is case-sensitive. clk, CLK, and Clk are three distinct identifiers. Keywords like module are always lowercase.
• Number format: size'base value. Example: 8'hFF = 8-bit hex = 255 decimal.
• Valid bases: b/B (binary), o/O (octal), d/D (decimal), h/H (hex). Base specifiers are case-insensitive.
• Decimal numbers do not support x or z digits. All other bases support x and z for unknown and high-impedance.
• Identifier rules: start with letter or _, contain letters/digits/_ /$. Cannot start with digit or $.
• Comments: // for single line, /* */ for block. Block comments cannot be nested.
• Key trap: Omitting size gives a 32-bit default. Specifying a smaller size than the value requires causes silent bit truncation.