Modeling Combinational Logic

Dataflow modeling in Verilog allows combinational logic to be described directly using Boolean equations and operators within assign statements. This approach sits between abstract behavioral code and low-level gate instantiation, making it both readable and synthesis-friendly for expressing combinational functions clearly.

Core Concept: Continuous Assignment and Combinational Logic

In Verilog, combinational logic is logic whose output depends only on current inputs with no memory of past states. Dataflow modeling captures this using the assign statement, which creates a continuous assignment. The right-hand side expression is continuously monitored, and any time an input changes, the output is immediately recalculated. This mirrors exactly how combinational hardware behaves.

Unlike procedural blocks such as always or initial, the assign statement does not need a sensitivity list. The simulator automatically tracks all variables on the RHS and re-evaluates whenever any of them change. Multiple assign statements execute in parallel and their order in the source file does not matter, reflecting the parallel nature of hardware.

Verilog Operators for Boolean Equations

Verilog provides bitwise operators that directly implement Boolean functions: & for AND, | for OR, ~ for NOT, ^ for XOR, and ~^ for XNOR. These operate bit-by-bit on their operands, making them suitable for both single-bit logic and multi-bit bus logic. Reduction operators such as &a apply the operation across all bits of a single vector, which is useful for parity or all-ones detection.

Modeling SOP and POS Expressions

Any Boolean function expressed in Sum of Products (SOP) or Product of Sums (POS) form translates directly to a Verilog assign statement. For example, a function F = AB + A'C maps to: assign F = (a&b) | (~a&c);. Similarly, a POS expression F = (A+B)(A'+C) maps to: assign F = (a|b) & (~a|c);. The synthesis tool reads these expressions and generates an optimized gate network in the target technology.

Modeling Standard Combinational Circuits

Common combinational circuits like adders, encoders, decoders, and comparators are easily modeled in dataflow style. A half adder uses: assign sum = a ^ b; assign carry = a & b;. A full adder extends this: assign sum = a ^ b ^ cin; assign cout = (a&b)|(b&cin)|(a&cin);. These concise equations are both functionally complete and directly synthesizable to standard cells.

Mathematical Expression

Boolean algebra directly governs the correctness of dataflow expressions. De Morgan's theorem, distribution, and absorption rules apply identically in Verilog and in hardware. For a function with N inputs, a correctly written assign statement produces output in O(1) propagation delay time (ignoring actual gate delays). The synthesis quality depends on how well the Boolean expression is minimized before writing the assign statement.

Given:
Design a 2:1 MUX with active-low enable using dataflow.
Inputs: a, b (data), sel (select), en_n (active-low enable)
Output should be 0 when disabled.

Why this formula applies:
Combinational output depends only on current inputs.
Active-low enable means enable is active when en_n=0.

Formula:
assign out = (~en_n) ? (sel ? b : a) : 1'b0;
Expanded: out = (~en_n & sel & b) | (~en_n & ~sel & a)

Substitution:
en_n=0, sel=1, a=0, b=1
~en_n = 1 (enabled), sel=1 → choose b

Calculation:
out = 1 & 1 & 1 = 1

Final Answer:
out = 1 (b selected, circuit enabled)

Exam Tip: In Verilog dataflow, multiple assign statements execute concurrently regardless of their order in the file. Changing their sequence does NOT change the simulation result. This is a common misconception tested in GATE questions.

Mechanism: How Continuous Assignment Works

• The assign keyword creates a driver on the LHS wire that continuously tracks the RHS expression.
• Any change on any RHS variable schedules a re-evaluation of the expression in the current time step.
• Multiple assign statements are all active simultaneously, just like parallel combinational gate networks.
• Bitwise operators &, |, ~, ^ operate independently on each bit position, enabling bus-wide logic without loops.
• The LHS of an assign must be a net type (wire), not a reg. Mixing reg with assign is a common syntax error.

Quick Revision

• assign statement models combinational logic with continuous evaluation — no sensitivity list needed.
• Operators: & (AND), | (OR), ~ (NOT), ^ (XOR), ~^ (XNOR), and reduction forms like &a.
• SOP: assign F = (a&b)|(~a&c); — POS: assign F = (a|b)&(~a|c);
• Half adder: sum = a^b; carry = a&b; — Full adder: sum = a^b^cin; cout = (a&b)|(b&cin)|(a&cin);
• LHS must be wire type. Assigning to reg with assign keyword is a syntax error.
• Order of multiple assign statements does NOT matter — they are all concurrent.
• Exam trap: Do not add sensitivity list to assign — it is not an always block and does not need one.