Verilog
Verilog Module Structure
Module, ports, endmodule, instance hierarchy.
Port Connection Rules
Input, Output, Inout, reg/wire connection rules.
FSM Behavioral Modeling
Mealy vs Moore coding styles.
Verilog Operators
Arithmetic, logical, bitwise, reduction, shift, concatenation.
Vectors and Arrays
Declaring buses, memories, reg [7:0] mem [0:255].
Data Types and Logic Values
Net (wire), Register (reg), 4-value logic (0,1,x,z).
Modeling Flip-Flops
D-FF, T-FF, JK-FF with async/sync resets.
Synchronous Memories
Modeling RAM/ROM with clock.
PLI Basics
Programming Language Interface C/C++ connection.
Simulation Time
Timescale directive, $time, $finish, $stop.
Verification Plan
Directed vs Random testing strategies.
Assertions
Introduction to SystemVerilog Assertions (SVA).
Randomization
Using $random for test vectors.
Modeling Comparators
Comparing vectors.
Switch Level Modeling
NMOS, PMOS, CMOS switches, transmission gates.
User Defined Primitives
Creating custom combinational/sequential primitives.
Delays in Dataflow
Inertial delay, transport delay.
Procedural Blocks
Always block, initial block, sensitivity lists.
Blocking vs Non-Blocking
Operators = vs <=, scheduling semantics.
Control Statements
If-else, case, casez, casex statements.
Timing Controls
Delay control #, event control @, wait statement.
Introduction to HDLs
Verilog vs VHDL, simulation vs synthesis.
Loops in Verilog
For, while, repeat, forever loops.
Block Statements
Begin-end, fork-join parallel blocks.
Task and Function
Subroutines, differences, automatic re-entrancy.
Continuous Assignment
Assign statement, implicit continuous assignment.
Conditional Operator
Modeling MUX using ternary operator.
Modeling Combinational Logic
Boolean equations using dataflow.
Gate Level Modeling
Built-in primitives (and, or, not), gate delays.
gate delays
Rise, fall, turn-off delays, min/typ/max.
Module Instantiation
Port mapping by order, by name.
Generate Blocks
Conditional and loop generate for scalable structures.
Modeling Latches
Level sensitive behavior, inferring latches accident.
Modeling Counters
Up/down counter, mod-N counter.
Modeling Shift Registers
SISO, SIPO, PISO, PIPO.
Modeling Multiplexers
Using if-else, case, assign statements.
Modeling Decoders/Encoders
Behavioral modeling of 3:8 decoder, priority encoder.
Modeling ALUs
Arithmetic Logic Unit implementation.
Modeling Adders
Half, Full, Ripple Carry Adder.
Testbench Basics
Stimulus, monitoring, checking results.
System Tasks
File I/O ($fopen), printing ($display, $monitor).
FPGA vs ASIC
Programmable logic vs fixed custom silicon.
Synthesis Concepts
RTL to Netlist translation.
Verilog 2001 Features
Signed arithmetic, generate, wildcards.
Lexical Conventions
Keywords, identifiers, numbers, whiteboard.