Modeling Decoders/Encoders

In digital systems, decoders and encoders are fundamental combinational circuits used to convert between different code formats. Decoders activate one of several outputs based on a binary input, while encoders do the reverse. Modeling these in Verilog using behavioral constructs builds strong intuition for both logic design and hardware description.

Core Concept: Decoder and Encoder Operation

A 3:8 decoder takes a 3-bit binary input and activates exactly one of its 8 output lines corresponding to the binary value of the input. For an input of 3b101 (decimal 5), only output Y[5] is asserted HIGH while all others remain LOW. This is essentially a minterm generator since each output corresponds to exactly one minterm of the input variables.

A priority encoder performs the reverse operation with an added twist. When multiple inputs are simultaneously HIGH, the encoder does not arbitrarily pick one. Instead, it assigns a fixed priority to each input line, typically from highest index to lowest, and outputs the binary code of the highest priority active input. A valid output indicator, often called the V or EO pin, goes HIGH whenever any input is asserted, which distinguishes a valid zero input from no input at all.

In Verilog, behavioral modeling means describing what the circuit does rather than how it is built from gates. The always block with a complete sensitivity list and case or if-else statements is the standard approach. For the decoder, a case statement maps each input combination to exactly one output. For the priority encoder, a cascaded if-else or casex structure handles input priority correctly.

Verilog Behavioral Model: 3:8 Decoder

The decoder is modeled using an always block sensitive to the input. A case statement covers all 8 input combinations and assigns the one-hot output accordingly. The output register is initially set to 8b0 before the case statement to ensure no latches are inferred for unspecified conditions.

The key Verilog construct here is one-hot encoding on the output side. When the input is 3b000, only Y[0] is HIGH, meaning out = 8b00000001. When input is 3b111, out = 8b10000000. The left shift operator can also produce this elegantly as out = 8b1 << in, which is a common GATE-level question on operator usage in Verilog.

Verilog Behavioral Model: Priority Encoder

A 4:2 priority encoder accepts a 4-bit input and produces a 2-bit binary output representing the position of the highest priority active bit. An additional valid output flag is asserted when at least one input is HIGH. The if-else if chain checks from the highest priority input downward, ensuring correct precedence.

A critical design detail is the handling of the valid signal. If all inputs are zero, the encoded output is 2b00 by default, which is identical to the encoding for input[0] being active. Without the valid flag, a downstream circuit cannot distinguish between these two cases. This detail is frequently tested in GATE and university examinations.

Mathematical Expression

For a 3:8 decoder, the Boolean expression for each output Yi is the product term (minterm) corresponding to the input A2A1A0. Specifically, the output corresponding to decimal index i is HIGH when the input binary value equals i. This gives Yi = mi where mi is the ith minterm. The one-hot property guarantees that exactly one output is HIGH for any given input, satisfying the condition that the sum of all outputs equals one for any valid input.

For an n-input priority encoder, the output is the binary representation of the index j of the highest priority HIGH input, where priority increases with index value. Mathematically, out = max(j) such that in[j] = 1. The valid signal V = OR of all inputs = in[0] | in[1] | ... | in[n-1].

Practical Understanding

Decoders are widely used in memory address decoding where a CPU provides an address and only one memory bank or peripheral must be selected at a time. In FPGA designs, decoders implement the address select logic for register files and multiplexed buses. The one-hot output of a decoder also directly feeds enable pins of multiple components.

Priority encoders are found in interrupt controllers of microprocessors. When multiple peripherals simultaneously request service, the interrupt controller uses a priority encoder to determine which request gets CPU attention first. The encoded output directly maps to the interrupt vector address. Modern processors use multiple levels of such encoders cascaded together.

Given:
4-input priority encoder with inputs in[3:0] = 4b1010
(in[3] = 1, in[2] = 0, in[1] = 1, in[0] = 0)

Why this formula applies:
Priority encoder selects the highest index active input.
in[3] = 1 which has highest priority among active inputs.

Formula:
out = binary index of highest active input
valid = OR of all inputs

Substitution:
Active inputs: in[3] and in[1] both HIGH
Highest priority input index = 3

Calculation:
out = 2b11 (binary for 3)
valid = in[3] | in[2] | in[1] | in[0] = 1|0|1|0 = 1

Final Answer:
out = 2b11, valid = 1
Meaning: input line 3 is the highest active input, output is valid.

Exam Tip: In Verilog, writing out = 8b1 << in; inside an always block models a decoder in one line. Also remember that a priority encoder without a valid flag cannot distinguish all-zero input from the lowest-priority active input. GATE often tests this case.

• The 3:8 decoder uses a case statement in Verilog; each case assigns a one-hot 8-bit output corresponding to the input minterm.
• The shift operation out = 8b1 << in is an elegant single-line behavioral model of a decoder and is commonly tested.
• The priority encoder uses cascaded if-else if blocks checking from the highest index input downward to enforce priority.
• The valid output must be asserted by OR-ing all input bits; it distinguishes valid zero output from no-input condition.
• For synthesis correctness, output registers in always blocks must be initialized before case or if-else to prevent latch inference.

Quick Revision

• 3:8 decoder: 3-bit input selects one of 8 outputs; only one output is HIGH at a time (one-hot output).
• Behavioral model uses always block with case statement or shift operation: out = 8b1 << in.
• Priority encoder: multiple HIGH inputs resolved by priority; highest index wins.
• Valid flag formula: V = in[0] | in[1] | in[2] | ... | in[n-1].
• Without valid flag, output 0 is ambiguous between no-input and lowest-priority input.
• Decoder output Yi = minterm mi; sum of all decoder outputs = 1 for any valid input.
• Exam trap: casex with don't cares models priority encoder but requires careful bit ordering to avoid incorrect priority.