Conditional Operator

The conditional operator in Verilog provides a compact and synthesizable way to describe multiplexer logic directly within dataflow modeling. It is one of the most commonly used operators in both RTL design and Verilog interviews, making it essential for any student targeting digital design roles or GATE examinations.

Core Concept: The Conditional Operator

The ternary operator in Verilog follows the syntax: assign out = condition ? true_expr : false_expr;. When the condition evaluates to 1 (true), out takes the value of true_expr. When the condition evaluates to 0 (false), out takes false_expr. If the condition is unknown (x or z), the output is a bitwise combination that may result in x in many bits.

This operator maps directly to hardware as a multiplexer. The condition signal acts as the select line, and the two expressions act as the two data inputs. This makes it the preferred way to model MUX behavior in dataflow style because synthesis tools directly infer MUX hardware from this construct.

Modeling a 2:1 MUX

A 2:1 MUX selects one of two inputs based on a select signal. Using the conditional operator: assign out = sel ? b : a;. When sel = 0, output is a. When sel = 1, output is b. This is functionally equivalent to the Boolean expression: out = (~sel & a) | (sel & b), but the conditional form is far more readable and synthesis-friendly.

Nesting for Higher-Order MUX

Conditional operators can be nested to model 4:1 or higher MUX structures. A 4:1 MUX can be written as: assign out = sel[1] ? (sel[0] ? d : c) : (sel[0] ? b : a);. Each nesting level adds one select bit and doubles the number of inputs considered. While this works correctly, deep nesting reduces readability and is better handled using always blocks for more than 4 inputs.

Behavior with Unknown Conditions

When the condition signal is x or z in simulation, the conditional operator does not simply pick one branch. Instead, it computes the output bit-by-bit: if the corresponding bit in true_expr and false_expr are the same, that bit is output; otherwise the output bit becomes x. This is a subtle but important simulation behavior that students often overlook.

Mathematical Expression

The Boolean equivalent of assign out = sel ? b : a; is the standard MUX equation: out = (sel AND b) OR (NOT sel AND a). Synthesis tools recognize the conditional operator and generate an optimized MUX cell from the target standard cell library. The critical path delay through this logic depends on the routing delay to the select input plus the MUX propagation delay.

Given:
A 4:1 MUX with select bits s1, s0 and inputs a, b, c, d.
Model using nested conditional operators.

Why this formula applies:
Each nesting level selects between two options based on one select bit.

Formula:
assign out = s1 ? (s0 ? d : c) : (s0 ? b : a);

Substitution:
s1=1, s0=0 → outer selects right branch (s0 ? d : c) → s0=0 → selects c

Calculation:
s1=1 → take (s0 ? d : c)
s0=0 → take c

Final Answer:
out = c when s1=1, s0=0

Exam Tip: When condition is x in Verilog conditional operator, the output is NOT x for all bits. Bits where true and false branches agree will still produce a known value. Only differing bits become x.

Mechanism: How Synthesis Interprets the Operator

• The synthesis tool reads assign out = sel ? b : a and maps it directly to a 2:1 MUX primitive or equivalent gate network.
• The condition signal sel becomes the select input S of the MUX hardware.
• The true_expr b connects to the I1 input and false_expr a connects to the I0 input of the MUX.
• Nested conditional operators produce cascaded or tree-structured MUX networks depending on the synthesis optimizer.
• The conditional operator is fully synthesizable and is preferred over if-else in dataflow assigns because it stays within a single assign statement.

Quick Revision

• Syntax: assign out = condition ? true_val : false_val; — maps directly to a MUX.
• condition=1 selects true_val, condition=0 selects false_val.
• 2:1 MUX: assign out = sel ? b : a; — sel is select line, a and b are data inputs.
• Nesting builds 4:1, 8:1 MUX structures, but readability drops with deep nesting.
• When condition is x: output is x only for bits where true and false branches differ.
• Exam trap: Conditional operator in assign is synthesizable. Do not confuse with if-else which requires always block.
• MUX Boolean equation: out = (sel AND b) OR (NOT sel AND a) — same result as conditional operator.