Modeling Comparators

A digital comparator is a combinational circuit that compares two binary vectors and produces outputs indicating whether one is equal to, greater than, or less than the other. In Verilog, comparators can be modeled with simple relational operators, making them an excellent example of how high-level behavioral constructs abstract complex gate-level logic. Understanding comparators is also essential for designing branch condition logic in processors.

Core Concept: Magnitude Comparison of Binary Vectors

Comparing two n-bit unsigned binary vectors requires determining their relative magnitude. The comparison proceeds from the most significant bit downward. The first bit position where A and B differ determines the outcome. If A[i] = 1 and B[i] = 0 at the most significant differing position, then A is greater than B. If all bits are equal, then A equals B.

In Verilog, this complex bit-by-bit logic is abstracted by the relational operators ==, >, and <. When applied to multi-bit vectors, Verilog automatically implements the full magnitude comparison logic. Declaring the comparator outputs as single-bit wires and using assign statements makes the model very concise. For example, assign eq = (a == b); captures the full equality check regardless of vector width.

The equality operator (==) in Verilog performs a bitwise comparison and returns 1 only when every bit of A matches the corresponding bit of B. The case equality operator (===) additionally handles X and Z values in simulation, which is important for testbench comparisons but should not be used in synthesizable design code.

Mathematical Expression

For two n-bit numbers A and B, the equality condition is: eq = AND of (A[i] XNOR B[i]) for all i from 0 to n-1. This checks that every bit pair is identical. The greater-than condition is more complex in gate-level logic: A > B is true when there exists a bit position k such that A[k] = 1, B[k] = 0, and for all positions j greater than k, A[j] equals B[j]. The less-than condition is simply lt = NOT(eq OR gt).

For signed comparison, the most significant bit (MSB) is the sign bit. Two positive numbers or two negative numbers are compared normally. When signs differ, the negative number is always smaller. In Verilog, signed comparison requires the $signed() system function or declaring the ports as signed type to invoke the correct arithmetic comparison.

Practical Understanding

Comparators are critical in processor branch units. Instructions like BLT (branch if less than) and BGE (branch if greater or equal) in RISC-V directly depend on magnitude comparison results. The comparator output drives the program counter multiplexer to select either the branch target address or the next sequential address. Timing of the comparator is on the critical path for branch resolution latency.

Cascaded comparators allow extending comparison width. A cascaded comparator accepts not just the two operands but also three cascade inputs (AEQB, AGTB, ALTB) from a lower-order comparator. The higher-order comparator checks the upper bits and uses the lower-order result only when the upper bits are equal. This architecture is the basis of the 74LS85 IC comparator chip frequently referenced in university examinations.

Given:
A = 4b1100 (decimal 12), B = 4b1100 (decimal 12)
Compare A and B using a 4-bit magnitude comparator.

Why this formula applies:
All bits of A and B are identical, so equality must be detected.
eq = AND(A[i] XNOR B[i]) for i = 3 downto 0

Formula:
eq = (A == B)
gt = (A > B)
lt = (A < B)

Substitution:
A[3:0] = 1100, B[3:0] = 1100
A[3] XNOR B[3] = 1 XNOR 1 = 1
A[2] XNOR B[2] = 1 XNOR 1 = 1
A[1] XNOR B[1] = 0 XNOR 0 = 1
A[0] XNOR B[0] = 0 XNOR 0 = 1

Calculation:
eq = 1 AND 1 AND 1 AND 1 = 1
gt = 0 (A not greater than B)
lt = 0 (A not less than B)

Final Answer:
eq = 1, gt = 0, lt = 0
A equals B: confirmed.

Exam Tip: In Verilog, == is the logical equality operator (returns 0 or 1); === is the case equality operator which also matches X and Z. Use == in synthesizable RTL; use === only in testbenches. Also, for signed comparison, you must use $signed(a) > $signed(b) or declare ports as signed, otherwise the comparison treats MSB as a magnitude bit and gives wrong results for negative numbers.

• Equality check: A[i] XNOR B[i] = 1 for each matching bit; eq = AND of all XNOR results.
• Greater-than: first differing MSB position where A=1 and B=0 asserts gt.
• Less-than: lt = NOT(eq OR gt); only one of eq, gt, lt can be HIGH at any time.
• Verilog assigns: assign eq = (a == b); assign gt = (a > b); assign lt = (a < b); are fully synthesizable.
• Signed comparison requires $signed() or signed port declaration; unsigned comparison of two's complement numbers gives wrong results for negative values.
• Cascaded comparator uses external EQ, GT, LT inputs from lower-order stage; IC 74LS85 is the classic example.

Quick Revision

• Comparator outputs: eq (A==B), gt (A>B), lt (A<B); exactly one is HIGH for any given input.
• Equality: eq = XNOR of each bit pair, all ANDed together.
• Verilog operator ==: bitwise equality, returns 1-bit result, fully synthesizable.
• Verilog operator ===: case equality, matches X and Z; use only in testbench, not in RTL.
• lt = NOT(eq OR gt) is always valid; saves one relational operator in synthesis.
• Signed comparison: use $signed(a) > $signed(b) to correctly handle two's complement.
• Exam trap: comparing two 4-bit vectors where both are 4b1000; unsigned gives 8>8=false, but 8 is a valid positive value. Signed interpretation gives -8 which changes the comparison result.