FSM Behavioral Modeling

Finite State Machines are the backbone of digital control logic in hardware design. In Verilog, FSMs are described using behavioral modeling, where the designer specifies state transitions and output logic using always blocks and case statements. Understanding how to correctly code Mealy and Moore machines in Verilog is a high-priority topic in both GATE and university examinations.

Core Concept: FSM Behavioral Modeling in Verilog

A Finite State Machine (FSM) is a sequential circuit that moves through a defined set of states based on input conditions. In Verilog behavioral modeling, FSMs are typically described using two or three always blocks: one for state memory (sequential), one for next-state logic (combinational), and optionally one for output logic. This separation is strongly recommended for clean, synthesis-friendly code.

In a Moore machine, outputs depend only on the current state. This means output values are stable and glitch-free since they only change at clock edges when the state register updates. Moore machines generally require more states than Mealy machines to perform the same function.

In a Mealy machine, outputs depend on both the current state and the current inputs. This allows Mealy machines to respond to inputs within the same clock cycle, meaning fewer states are needed. However, outputs may glitch if inputs change asynchronously, since the combinational output logic reacts immediately to input changes.

Verilog Coding Style for FSMs

The standard three-always-block style in Verilog separates concerns clearly. The first always block is a clocked sequential block that updates the current state register on the clock edge. The second always block is a combinational block using a case statement to compute the next state based on current state and inputs. The third always block handles output logic — for Moore this is purely state-based, and for Mealy it also uses input signals inside the case statement.

State encoding is another important design choice. Binary encoding uses the minimum number of flip-flops but may lead to more complex next-state logic. One-hot encoding assigns one flip-flop per state, resulting in simpler next-state logic and faster synthesis on FPGAs. Gray encoding minimizes transitions between adjacent states and is useful when power is a concern.

Mathematical Expression

For a Moore machine with state set S, input alphabet I, and output alphabet O, the behavior is defined by a next-state function and an output function. The next-state function is written as NS = f(CS, IN), where CS is the current state and IN is the current input. The output function for Moore is OUT = g(CS), while for Mealy it is OUT = g(CS, IN). These two equations directly correspond to the combinational always blocks in Verilog code.

Practical Understanding

Consider a sequence detector that detects the pattern 1011 on a serial input line. Implementing this as a Moore machine requires five states: one idle state and four states tracking progress through the pattern. The output goes high only when the last state (pattern matched) is entered. In a Mealy implementation, the output can be asserted in the transition itself, reducing the state count to four.

In practice, synthesis tools handle both styles well. The choice between Moore and Mealy is driven by functional requirements: if glitch-free outputs are critical (for example, driving an asynchronous reset or enable), Moore is preferred. If minimizing state count or achieving faster response is the goal, Mealy is chosen.

Numerical Example: State Count Comparison

Given:
Sequence to detect: 1011 (overlapping detection)
Moore machine states needed: 5 (S0 to S4)
Mealy machine states needed: 4 (S0 to S3)

Why this formula applies:
Mealy machines can produce output on transitions, eliminating the need for a dedicated output state.

Formula:
Moore states = Mealy states + 1 (for a single-output sequence detector)

Substitution:
Moore = 4 + 1 = 5 states
Mealy = 4 states

Calculation:
Flip-flops for Moore: ceil(log2(5)) = 3 flip-flops
Flip-flops for Mealy: ceil(log2(4)) = 2 flip-flops

Final Answer:
Moore requires 3 flip-flops; Mealy requires 2 flip-flops for 1011 detector.

Exam Tip: In GATE, if a question asks for minimum states in a sequence detector, the Mealy answer is always one less than Moore. Also, if outputs are specified on state transitions in a state diagram, it is a Mealy machine — this is a common identification trap.

Quick Revision

• Moore machine: output = g(current state) only. Outputs change only at clock edge. Glitch-free.
• Mealy machine: output = g(current state, input). Output reacts to input immediately. Fewer states needed.
• Three-block FSM coding style: sequential state register block, combinational next-state block, combinational output block.
• State encoding options: binary (minimum flip-flops), one-hot (FPGA-friendly), Gray (low transitions).
• Formula: Moore states = Mealy states + 1 for sequence detectors.
• Flip-flop count = ceil(log2(number of states)) for binary/Gray encoding.
• Common trap: output on transition arrow in a state diagram means Mealy machine, not Moore.