Modeling Latches

In Verilog, sequential circuits are modeled using always blocks that respond to signal changes. A latch is a level-sensitive storage element that holds its output as long as the enable signal is active. Understanding how latches are inferred is critical for both correct RTL design and GATE preparation.

Core Concept: Level Sensitivity and Latch Behavior

A latch differs from a flip-flop in one fundamental way: it responds to the level of its enable signal, not the edge. When EN is high, the output Q follows D directly. When EN goes low, Q retains its last captured value regardless of changes on D. This is the defining characteristic of level-sensitive sequential logic.

In Verilog, a latch is typically inferred when an always block uses a combinational sensitivity list but does not assign the output for every possible input condition. The synthesis tool detects that in some cases the output must retain its old value, and it inserts a latch to satisfy that requirement. This is often unintentional and is considered a design bug in most RTL workflows.

The most common cause of accidental latch inference is an incomplete if-else statement or a case statement missing a default clause. For example, if an if block assigns q only when en is high but has no else clause, the synthesis tool concludes that q must hold its value when en is low, which implies a latch. This is why synthesis warnings about latches must never be ignored.

Intentional Latch Modeling in Verilog

When a latch is intentionally required, it can be modeled cleanly using a straightforward always block. The sensitivity list must include both the data input and the enable signal. The assignment is made conditionally on the enable. No else clause is written, which is precisely what tells synthesis to infer a latch rather than combinational logic.

The Verilog code for a positive-enable D latch is written as: always @(en or d) if (en) q <= d;. If instead you write always @(posedge clk), the synthesis tool will target a flip-flop. The distinction between posedge-triggered and level-triggered behavior begins at the sensitivity list itself.

Accidental Latch Inference — The Dangerous Case

Consider a 2-to-1 multiplexer written with an if-else inside an always block. If the else condition is missing, the synthesis tool sees that when sel is neither 0 nor 1 (in a case with more conditions) or simply when the output is not covered for all inputs, a latch is inserted. In simulation, this may go unnoticed because simulation does not always model the latch delay or glitch propagation.

To prevent accidental latches: always write complete if-else chains, always include a default in every case statement, and review synthesis reports for any latch inference warning. In FPGA designs, latches can cause hold-time violations and glitches, making them particularly problematic in high-speed designs.

Mathematical Expression

The characteristic equation of a D latch is: Q_next = D when EN = 1, and Q_next = Q (hold) when EN = 0. This can be expressed as Q_next = EN.D + EN_bar.Q. This equation shows that the output is a function of the present state Q when enable is low, confirming the sequential memory nature of the latch.

Practical Understanding

Latches are used in real designs in cases such as clock gating cells, where a latch-based clock gate is preferred over a flip-flop-based one for glitch-free clock control. They also appear in data path designs where partial write operations on memories require holding partial results. However, in general RTL design for ASICs and FPGAs, latches are strongly discouraged because static timing analysis tools handle them differently from flip-flops and they can cause setup and hold timing uncertainty.

Given:
A D latch with EN = 1, D transitions: 0 -> 1 -> 0 -> 1
EN then goes to 0 while D = 1

Why this formula applies:
Q follows D when EN=1 (transparent mode); Q holds last value when EN=0

Formula:
Q_next = EN.D + EN_bar.Q

Substitution (EN=0, last D captured = 1):
Q_next = 0.D + 1.Q = Q = 1

Calculation:
EN=1, D=0 -> Q=0
EN=1, D=1 -> Q=1
EN=1, D=0 -> Q=0
EN=1, D=1 -> Q=1
EN=0, D=1 -> Q holds = 1
EN=0, D=0 -> Q holds = 1 (D change ignored)

Final Answer:
Q = 1 (latch holds last captured value when EN=0)

Exam Tip: If an always block with a combinational sensitivity list does not assign output for every input combination, synthesis infers a latch — not a flip-flop. GATE questions frequently test this distinction. A missing else or missing default is the trigger.

Latch Inference Mechanism

• A latch is inferred when an always block has a combinational sensitivity list and does not assign the output for all possible input combinations.
• The characteristic equation Q_next = EN.D + EN_bar.Q describes level-sensitive hold behavior mathematically.
• Intentional latch: write always @(en or d) and use if(en) q<=d with no else clause.
• Accidental latch: any incomplete if-else or case without default in a combinational always block.
• Always review synthesis log for latch inference warnings before proceeding to simulation.

Quick Revision

• Latch: level-sensitive storage; Q follows D when EN=1, holds when EN=0.
• Characteristic equation: Q_next = EN.D + EN_bar.Q.
• Inferred by synthesis when always block does not cover all output paths.
• Missing else or missing default in case = accidental latch — common GATE trap.
• Flip-flop uses posedge/negedge in sensitivity list; latch uses level signals.
• Latches are avoided in RTL design; they cause STA complications and glitch issues.
• Exam trap: a case block without default always infers a latch when used in a combinational always block.