Modeling Counters

Counters are among the most widely used sequential circuits in digital design, forming the backbone of timers, address generators, control sequencers, and communication protocols. In Verilog, modeling counters requires a clear understanding of how clocked always blocks, synchronous reset, and modular counting work together to produce reliable synthesizable RTL.

Core Concept: Counting with Clocked Always Blocks

All synthesizable counters in Verilog are built inside always @(posedge clk) blocks. On each rising edge of the clock, the count register is updated according to the counter type. A synchronous reset is placed as the first condition inside the always block, ensuring that the reset operation itself is registered and glitch-free, which is the recommended practice in standard RTL design.

An up counter simply increments the count register by 1 on every clock edge. Since Verilog handles register overflow naturally (a 4-bit counter overflows from 15 back to 0 automatically), no explicit wrap-around logic is needed for a standard binary counter. A down counter decrements by 1 and wraps from 0 to the maximum value due to unsigned underflow.

An up/down counter includes a direction control signal, often named up_down or dir. When this signal is high, the counter increments. When low, it decrements. The always block uses an if-else on this direction signal inside the clocked block, after the reset check. This is the standard pattern used in most textbooks and RTL coding guidelines.

Mod-N Counter: Controlled Rollover

A Mod-N counter counts from 0 to N-1 and then resets to 0 on the next clock edge. It does not rely on natural binary overflow. Instead, an explicit comparison checks whether the count has reached N-1, and if so, the count is reset to 0 synchronously. This makes the counter count through exactly N distinct states.

The Verilog pattern for Mod-N is: inside the always block, after the reset condition, write if (count == N-1) count <= 0; else count <= count + 1;. The width of the count register must be at least ceil(log2(N)) bits to hold the maximum value N-1 without truncation.

Mathematical Expression

For a Mod-N counter, the required bit width is given by: W = ceil(log2(N)). The counter cycles through N states: 0, 1, 2, ..., N-1, then returns to 0. The number of distinct count values equals N, not 2^W unless N is a power of 2. The period of the counter output in clock cycles equals N, which is directly useful for frequency division: f_out = f_clk / N.

Practical Understanding

Counters are used in almost every digital system. Address counters in memory controllers, program counters in processors, baud rate generators in UARTs, PWM period counters in motor drives, and event counters in measurement systems all depend on the Mod-N counting principle. In FPGA designs, counters consume flip-flop resources proportional to their bit width, so sizing them correctly saves area.

Synchronous reset is preferred over asynchronous reset in most ASIC and FPGA flows because it avoids timing complications related to metastability and reset recovery time. Asynchronous reset involves the reset signal in the sensitivity list as posedge rst, while synchronous reset keeps the sensitivity list as posedge clk only and checks rst inside the block.

Given:
Mod-6 counter, clock frequency = 12 MHz

Why this formula applies:
Mod-N counter divides clock by N; output toggles every N clock cycles

Formula:
f_out = f_clk / N
Bit width W = ceil(log2(N))

Substitution:
N = 6, f_clk = 12 MHz
f_out = 12 MHz / 6
W = ceil(log2(6)) = ceil(2.585) = 3 bits

Calculation:
f_out = 2 MHz
Count register needs 3 bits (holds 0 to 7, but resets at 5)

Final Answer:
Output frequency = 2 MHz, register width = 3 bits (reg [2:0] count)

Exam Tip: For a Mod-N counter, the bit width is ceil(log2(N)), not log2(N). For N=8, W=3 exactly. For N=6, W=3 (not 2.58). GATE questions often ask for minimum bits required — always take ceiling.

Counter Mechanics and State Transitions

• Mod-N counter resets when count == N-1; requires ceil(log2(N)) bit register.
• Up counter increments on posedge clk; down counter decrements; up/down uses direction signal.
• Synchronous reset is checked inside posedge clk block; keeps timing analysis clean.
• Frequency division: f_out = f_clk / N for Mod-N counter.
• Missing reset-to-zero condition in Mod-N counter causes incorrect rollover to 2^W instead of N.

Quick Revision

• Counter always block: always @(posedge clk) with synchronous reset as first condition.
• Up counter: count <= count + 1; Down counter: count <= count - 1.
• Mod-N: if(count == N-1) count <= 0; else count <= count + 1.
• Bit width formula: W = ceil(log2(N)) — ceiling is mandatory.
• Frequency division: f_out = f_clk / N.
• Exam trap: using W = log2(N) without ceiling gives wrong bit width for non-power-of-2 N.
• Synchronous reset preferred over asynchronous in ASIC/FPGA RTL.