BCD Counter

BCD counters are inside every digital clock, calculator, and seven-segment display driver. They count from 0 to 9 and then reset, making decimal output possible without binary-to-decimal software conversion.

Core Concept

A BCD counter counts in Binary Coded Decimal, cycling through states 0000 to 1001 (0 to 9) and then resetting. States 1010 through 1111 are unused and are called invalid or forbidden states.

The 74LS90 is a classic decade counter. It has a built-in divide-by-2 (QA) and divide-by-5 (QB QC QD) section. Connecting QA to the clock of the divide-by-5 section creates the BCD sequence. Its clock frequency limit is 32 MHz, power consumption is 45 mW, and it operates at 5 V.

A simpler approach uses a 4-bit binary counter like the 74LS163 with an external NAND gate detecting state 10 (Q3·Q1) and asserting the synchronous load or clear. Because the clear is synchronous on the 74LS163, there is no output glitch. Asynchronous clear on older counters like the 74LS90 produces a brief glitch at state 10.

Boolean Expression

The reset condition for a BCD counter is CLR = Q3 · Q1. State 10 is the first state with both Q3=1 and Q1=1 simultaneously. No valid BCD state has this combination, so false triggering is impossible within the count sequence.

Using minterms, the 10 valid states are m0 through m9. The six invalid states (m10–m15) are don't-cares in any K-map used to design the BCD counter logic.

Given:
Design BCD counter reset using 74LS163 with synchronous clear (active low).
Detect state 10 (1010) and force load of 0000.

Formula / Rule:
State 10 = Q3Q2Q1Q0 = 1010
Detect: Q3=1 and Q1=1 (Q2=0 and Q0=0 also true but unnecessary)
Minimum detection: CLR_bar = NAND(Q3, Q1)

Step by step:
Count 8  (1000): Q3=1,Q1=0 => NAND output=1 (no reset)
Count 9  (1001): Q3=1,Q1=0 => NAND output=1 (no reset)
Count 10 (1010): Q3=1,Q1=1 => NAND output=0 => CLR_bar=0
  74LS163 synchronous clear: at next clock edge, Q3Q2Q1Q0 -> 0000
  State 1010 is never latched; counter goes 9->0000 cleanly

Final Answer:
Connect one 74LS00 NAND gate: inputs Q3 and Q1, output to CLR_bar of 74LS163.
Counter cycles 0-1-2-3-4-5-6-7-8-9-0 with no glitch.

Exam Tip: GATE questions often ask whether a glitch appears at state 10. With asynchronous clear (74LS90 style), state 1010 appears briefly on the output before being cleared — this is a real hazard. With synchronous clear (74LS163), the state 1010 is never latched because the clock edge and clear happen together. Always state whether the reset is synchronous or asynchronous when answering.

Key Properties

• 74LS90: divide-by-2 and divide-by-5 sections, 32 MHz max clock, 45 mW, 5 V
• 74HC4017: Johnson decade counter/divider, CMOS, 2–6 V, 10 decoded outputs
• BCD has 10 valid states; 6 invalid states (1010–1111) are don't-cares in design
• Minimum reset gate: NAND(Q3, Q1) — uses only two inputs, one gate
• Two 74LS90s cascaded (units and tens) form a mod-100 BCD counter
• 74LS90 asynchronous clear produces a glitch; 74LS163 synchronous clear does not
• BCD output drives 7447 or 74LS47 BCD-to-seven-segment decoder directly

Quick Revision

• BCD counter: 10 states (0000 to 1001), resets on state 1010
• Reset gate: CLR = Q3 · Q1 (two-input AND or NAND with active-low clear)
• 74LS90 uses asynchronous clear — state 1010 glitches briefly
• 74LS163 with synchronous CLR avoids the glitch at state 10
• States 1010–1111 are invalid; treat as don't-cares in K-maps
• Cascade two BCD counters for decades: units carry-out clocks tens counter
• 74LS47 decodes BCD to seven-segment; ripple blanking pin (RBI) blanks leading zeros
• Exam trap: Using CLR = Q3·Q2 detects state 12, not 10 — always verify which bits are 1 in the reset state