Signed Number Representation

Signed number representation determines how CPUs interpret and compare integers. The choice of representation affects the design of comparators, branch instructions, and flag registers in processors like the Intel 8086 and ARM Cortex-A series.

Core Concept

Four methods exist for representing signed integers in binary. Sign-magnitude stores the sign in the MSB and the magnitude in the remaining bits. It is intuitive but requires separate addition and subtraction hardware and has two zeros.

1s complement and 2s complement both encode the sign implicitly through the bit pattern. 2s complement is the universal standard in all modern CPUs because it has a single zero, supports simple addition/subtraction with one hardware unit, and simplifies overflow detection. The ARM Cortex-M4 APSR flags (N, Z, C, V) are designed around 2s complement arithmetic.

The fourth method, excess-N or biased notation, stores the value as (true value + N). Excess-127 is used for the exponent field of the IEEE 754 single-precision float. Biased encoding allows unsigned comparators to sort signed values directly, which is why it is used inside floating-point units.

Boolean Expression

For an n-bit 2s complement number with bits bₙ₋₁ ... b₁ b₀: value = −bₙ₋₁ × 2ⁿ⁻¹ + Σᵢ₌₀ⁿ⁻² bᵢ × 2ⁱ. For sign-magnitude: value = (−1)^bₙ₋₁ × (bₙ₋₂...b₀). For excess-N: value = code − N.

Given:
  Identify the decimal value of 10110010 in each representation

Formula / Rule:
  Apply the appropriate formula for each format

Step by step:

  Sign-Magnitude:
    MSB=1 means negative. Magnitude = 0110010 = 50
    Value = -50

  1s Complement:
    MSB=1 means negative.
    Invert all bits: 01001101 = 77
    Value = -77

  2s Complement:
    MSB=1 means negative.
    Invert and add 1: 01001101 + 1 = 01001110 = 78
    Value = -78
    (Or: -128 + 32 + 16 + 2 = -78)

  Excess-127 (IEEE float exponent):
    Binary 10110010 = 178 unsigned
    Value = 178 - 127 = +51

Final Answer:
  Same bit pattern 10110010 means:
  SM: -50,  1sC: -77,  2sC: -78,  Excess-127: +51

Exam Tip: GATE problems regularly ask you to convert the same bit pattern under different signed representations. The three methods give three different values for any pattern with MSB=1. Also, the range of 2s complement is asymmetric: minimum is -2^(n-1), maximum is +2^(n-1)-1. For 8 bits: -128 to +127. Many students incorrectly state the range as -127 to +127.

Key Properties

• Sign-magnitude: MSB = sign, rest = magnitude; range -(2ⁿ⁻¹-1) to +(2ⁿ⁻¹-1); two zeros
• 1s complement: negate by inverting all bits; two zeros; needs end-around carry
• 2s complement: negate by inverting + adding 1; one zero; range -2ⁿ⁻¹ to +2ⁿ⁻¹-1
• Excess-N: value = stored_code − N; used in IEEE 754 exponent field with N=127 (single) or N=1023 (double)
• 2s complement is standard in ARM Cortex, x86, 8051, 8085, RISC-V, and all modern DSPs
• Overflow in 2s complement: adding two same-sign numbers yields opposite-sign result
• IEEE 754 single precision: 1 sign bit, 8 biased exponent bits (excess-127), 23 mantissa bits

Quick Revision

• Sign-magnitude: MSB is sign, not part of value
• 1s complement negate: flip all bits; 2s complement negate: flip all bits + 1
• 1s and sign-magnitude both have two zeros; 2s complement has one
• 2s complement range (n-bit): -2^(n-1) to +2^(n-1)-1
• Excess-127 used for IEEE 754 float exponent; allows direct unsigned comparison
• All modern CPUs: 2s complement for integers
• ARM APSR V flag signals 2s complement signed overflow
• Exam trap: many students state 8-bit range as -127 to +127 — the correct range is -128 to +127