3-to-8 Decoder

The 3-to-8 decoder inside every 8086 memory interface converts three address lines into eight chip-enable signals, allowing eight separate memory ICs to share one address bus. The 74HC138 is the standard part for this task.

Core Concept

Three input bits encode 2^3 = 8 unique addresses. The decoder asserts exactly one output for each address. On the 74HC138, that assertion is active-low: the selected output goes to logic 0. All non-selected outputs stay at logic 1. No two outputs are ever simultaneously active.

The 74HC138 has three enable pins: E1 (active-high), E2 (active-low), and E3 (active-low). All three must be satisfied simultaneously—E1=1, E2=0, E3=0—to enable the chip. Propagation delay is 9 ns at 5 V. Fan-out: 10 HC loads. Supply: 2 V to 6 V. Power: ~0.1 mW static.

Two 74HC138 ICs can form a 4-to-16 decoder. Connect A, B, C to both chips. Use a fourth address bit A3: feed it directly to E1 of the second chip, and through an inverter to E1 of the first chip. Each chip activates for exactly half the address space.

Boolean Expression

Each output is the complement of one 3-variable minterm. Yn_bar = NOT(minterm n of C,B,A). So Y0_bar = NOT(C'B'A'), Y3_bar = NOT(C'BA), Y7_bar = NOT(CBA). In SOP form, the active-low output equals the sum of all minterms except n. This is why decoders implement any Boolean function directly: OR the required active-low outputs through a NAND gate.

Given:
  C=1, B=0, A=1 (address = 5), all enables satisfied

Formula:
  Y_bar_n = NOT(minterm n)
  Y_bar_5 = NOT(C . B' . A)

Step by step:
  B' = NOT(0) = 1

  minterm 5 = C.B'.A = 1.1.1 = 1
  Y_bar_5 = NOT(1) = 0  --> Y5 goes LOW (asserted)

  All others:
  minterm 0 = 0.1.0 = 0 --> Y_bar_0 = 1 (inactive)
  minterm 7 = 1.1.1 but address is 101 so minterm 7 = C.B.A = 1.0.1 = 0 --> Y_bar_7 = 1
  (Similarly Y0..Y4, Y6, Y7 remain high)

Final Answer:
  Y5 = 0 (active, low), Y0-Y4, Y6, Y7 = 1 (inactive)

Exam Tip: GATE 2019 EC asked to implement a Boolean function using a 3-to-8 decoder and external OR gates. The method: write the function in minterm form, then OR the active-low outputs of those minterms through a NAND gate (NAND of active-lows = NOR of active highs = OR of original minterms). This is a standard exam question type for VTU and Anna University too.

Key Properties

• IC: 74HC138, also 74LS138 (TTL, 22 ns delay, 4.75–5.25 V supply)
• Outputs: active-low; 74HC238 is the active-high equivalent
• Propagation delay: 9 ns (74HC138 at 5 V), 22 ns (74LS138)
• Three enable pins: E1 active-high, E2 and E3 active-low
• Fan-out: 10 HC loads or 5 LS-TTL loads
• Can implement any 3-variable Boolean function using external NAND gate
• Two chips cascaded with A3 form a complete 4-to-16 decoder

Quick Revision

• 3-to-8 decoder: 3 inputs → 8 mutually exclusive active-low outputs
• Yn_bar = complement of minterm n in C, B, A
• 74HC138: enable requires E1=1, E2=0, E3=0 simultaneously
• Any 3-variable Boolean function: select minterms, NAND those outputs
• Widely used in 8085/8086 memory bank chip-select generation
• Cascade two 74HC138 to build 4-to-16 decoder using fourth address line
• Exam trap: assuming outputs are active-high on 74HC138—they are active-low; select 74HC238 for active-high