Universal Gates NAND

Every digital IC family — TTL, CMOS, ECL — can be built using only NAND gates. The 7400 quad 2-input NAND is the single most manufactured logic IC in history.

Core Concept

A universal gate can implement any Boolean function on its own, without any other gate type. The NAND gate is universal because NOT, AND, and OR — the three primitives of Boolean algebra — can each be built using only NAND gates.

The IC 7400 contains four independent 2-input NAND gates in a 14-pin DIP package. At 5 V, propagation delay is 9 ns, fan-out is 10 standard TTL loads, and quiescent power per gate is about 2 mW. The 74LS00 (low-power Schottky) cuts power to 0.5 mW with 9.5 ns delay.

De Morgan's theorem ties NAND to OR-invert: (AB)' = A' + B'. This means a NAND gate with inverted inputs behaves as OR. This equivalence is the reason NAND naturally maps to SOP (sum of products) logic — the standard form for most combinational circuit design.

Boolean Expression

NAND output: Y = (A · B)'. Derived gates: NOT = NAND(A,A). AND = NAND(NAND(A,B), NAND(A,B)). OR = NAND(NAND(A,A), NAND(B,B)). XOR requires 4 NAND gates: a classic exam derivation.

Given:
  Implement OR gate using only NAND gates
  Inputs: A, B

Formula / Rule:
  A + B = A' NAND B'  (De Morgan)
  A' = NAND(A, A)
  B' = NAND(B, B)
  A' NAND B' = NAND(NAND(A,A), NAND(B,B))

Step by step (A=1, B=0):
  Gate 1: NAND(A, A) = NAND(1,1) = 0  (this is A')
  Gate 2: NAND(B, B) = NAND(0,0) = 1  (this is B')
  Gate 3: NAND(0, 1) = 1              (this is A' NAND B')

  Expected OR(1,0) = 1 --> matches!

Step by step (A=0, B=0):
  Gate 1: NAND(0,0) = 1  (A'=1)
  Gate 2: NAND(0,0) = 1  (B'=1)
  Gate 3: NAND(1,1) = 0  --> OR(0,0)=0 -- matches!

Final Answer:
  OR gate requires 3 NAND gates
  AND gate requires 3 NAND gates (NAND then NOT)
  NOT gate requires 1 NAND gate (tie both inputs)

Exam Tip: The minimum NAND gate count is tested heavily. NOT = 1 NAND, AND = 2 NAND (wrong if you count 3 — you combine the final NOT into the NAND itself only for specific topologies). OR = 3 NAND (two inverters then one NAND). XOR and XNOR each = 4 NAND gates. Memorize these counts. Also: a 2-input NAND with one input tied HIGH acts as an inverter — this is used in IC 7400 to save a package when only one spare gate is available.

Key Properties

• IC 7400: quad 2-input NAND, 14-pin DIP, propagation delay 9 ns at 5 V
• 74LS00: low-power Schottky, 9.5 ns, 0.5 mW per gate, fan-out 20
• 74HC00: CMOS NAND, 7 ns at 5 V, 2–6 V supply, 80 µW per package
• Fan-out: 10 standard TTL loads for 7400; 20 for 74LS00
• NOT from NAND: 1 gate (both inputs tied together)
• OR from NAND: 3 gates (two inverters + one NAND) using De Morgan
• XOR from NAND: 4 gates (classic exam derivation)

Quick Revision

• NAND is universal: can implement any Boolean function alone
• Y = (AB)' — output LOW only when both inputs are HIGH
• De Morgan: (AB)' = A' + B' — NAND = OR with inverted inputs
• NOT = 1 NAND, AND = 2 NAND, OR = 3 NAND, XOR = 4 NAND
• 7400: 9 ns, 5 V, 10 fan-out; 74LS00: 9.5 ns, 0.5 mW, 20 fan-out
• SOP (sum of products) maps naturally to two-level NAND-NAND logic
• One input tied HIGH makes 2-input NAND act as inverter
• Exam trap: AND from NAND requires only 2 gates total, not 3 — the NAND itself is reused when the AND output is used as an intermediate