CMOS Logic Family

CMOS logic powers every modern microprocessor, from the ARM cores in your phone to the FPGAs used in 5G base stations. Understanding how complementary MOS transistor pairs create logic gates is foundational to any serious digital design career.

Core Concept

CMOS stands for Complementary Metal-Oxide-Semiconductor. Every CMOS gate pairs a PMOS transistor network (connected to VDD) with an NMOS transistor network (connected to GND). For any input combination, exactly one network is ON and the other is OFF. This means no DC current path exists between VDD and GND in steady state, giving CMOS its hallmark near-zero static power dissipation.

The 74HC04 hex inverter is a classic example. It operates from 2V to 6V, has a propagation delay of about 7 ns at 5V, and can drive a fan-out of 10 standard CMOS loads. The CD4069UB is the unbuffered CMOS variant rated for 3V to 15V supply, used in analog and oscillator applications. Dynamic power dissipation does occur during switching: P = C·VDD²·f, which is why power grows linearly with clock frequency.

CMOS gates are built by dualizing networks. The NMOS pull-down network for an AND gate has transistors in series. The PMOS pull-up network is the dual: transistors in parallel. This duality rule lets you design any static CMOS gate directly from the Boolean function without trial and error.

Boolean Expression

For the CMOS NAND gate: Y = (A·B)'. The NMOS pull-down has A and B transistors in series (both must be ON to pull output low). The PMOS pull-up has A and B transistors in parallel (either being OFF pulls output high). This structural mapping is universal: series NMOS ↔ parallel PMOS, parallel NMOS ↔ series PMOS. The 74HC00 quad NAND implements this at tpd ≈ 8 ns and fan-out of 10.

Given:
CMOS NAND gate with inputs A=1, B=0

Formula / Rule:
Y = (A · B)'
NMOS network: A and B in series → both must be 1 for pull-down to conduct
PMOS network: A and B in parallel → either 0 turns on pull-up

Step by step:
Step 1: A · B = 1 · 0 = 0   (NMOS series — at least one OFF, pull-down OFF)
Step 2: PMOS B transistor: gate=0 → PMOS ON (VGS < Vtp)
Step 3: Output node connects to VDD through PMOS B
Step 4: Y = (A · B)' = (0)' = 1

Final Answer:
Y = 1  (output is logic HIGH, ≈ VDD)

Exam Tip: GATE often asks why CMOS has near-zero static power but TTL does not. TTL always has a resistor between VCC and ground in the totem-pole output, creating a small steady current. CMOS has no such DC path. Also remember: dynamic power P = C·VDD²·f applies to CMOS — doubling frequency doubles power. A common trap is confusing the PMOS pull-up network topology (dual of NMOS) — always apply the duality rule: series becomes parallel and vice versa.

Key Properties

• Static power dissipation: ~0 nW (no DC path between VDD and GND in steady state)
• Dynamic power: P = C·VDD²·f — 74HC family at 5V, 10 MHz, 15 pF load ≈ 3.75 mW per gate
• Supply voltage: 74HC series: 2V–6V; CD4000 series: 3V–18V
• Propagation delay: 74HC04 ≈ 7 ns at 5V; CD4069 ≈ 60 ns at 5V (slower, older process)
• Fan-out: 74HC ≥ 10 CMOS loads; input current < 1 µA (high impedance gate oxide)
• Noise margin: ~30% of VDD, typically 1.0V at 3.3V supply — better than TTL at low voltages
• Logic family: CMOS (74HC, 74HCT, 74AC, 74ACT, CD4000) — HCT is TTL-input compatible

Quick Revision

• CMOS uses complementary PMOS (pull-up) and NMOS (pull-down) transistor networks
• In steady state, only one network conducts — static power ≈ 0
• NMOS pull-down network topology is dual of PMOS pull-up: series ↔ parallel
• Dynamic power P = C·VDD²·f — proportional to frequency and square of supply voltage
• 74HC04 (inverter): tpd ≈ 7 ns, VDD 2–6V, fan-out 10; CD4069: tpd ≈ 60 ns, VDD 3–18V
• 74HCT series is designed for TTL-compatible input levels (VIH min = 2.0V)
• Noise margin improves as VDD increases — CMOS is preferred for noisy industrial environments
• Exam trap: assuming CMOS has zero power at high frequencies — dynamic power grows with f and VDD²