Universal Gates NOR

PLC ladder logic, fail-safe relay circuits, and fault-tolerant memory all prefer NOR-based implementations. The 7402 quad NOR IC is the NAND gate's equally powerful twin.

Core Concept

The NOR gate is also a universal gate — every Boolean function can be realized using NOR alone. The IC 7402 contains four 2-input NOR gates in a 14-pin DIP. Propagation delay is 10 ns at 5 V, fan-out is 10 TTL loads, and power per gate is 2.4 mW.

De Morgan's theorem for NOR states: (A + B)' = A' · B'. This means NOR with inverted inputs behaves as AND. This equivalence makes NOR the natural gate for POS (product of sums) expressions — the standard form used in NAND-NOR two-level synthesis with NOR.

The 74HC02 (CMOS version) operates from 2 V to 6 V with a propagation delay of 8 ns at 5 V and near-zero static power. In CMOS memory sense amplifiers and domino logic, NOR structures are preferred because pull-down NMOS stacks are faster than pull-up PMOS chains — the electrical dual of why NAND is preferred in standard CMOS gates.

Boolean Expression

NOR output: Y = (A + B)'. Derived gates: NOT = NOR(A,A). OR = NOR(NOR(A,B), NOR(A,B)). AND = NOR(NOR(A,A), NOR(B,B)). Each uses the same count as NAND implementations but applied to POS logic.

Given:
  Implement AND gate using only NOR gates
  Inputs: A, B

Formula / Rule:
  A.B = (A'+B')'  (De Morgan)
  A' = NOR(A,A), B' = NOR(B,B)
  (A'+B')' = NOR(A', B')

Step by step (A=1, B=1):
  Gate 1: NOR(A,A) = NOR(1,1) = 0  --> A'=0
  Gate 2: NOR(B,B) = NOR(1,1) = 0  --> B'=0
  Gate 3: NOR(0,0) = 1             --> AND(1,1)=1 -- correct!

Step by step (A=1, B=0):
  Gate 1: NOR(1,1) = 0  --> A'=0
  Gate 2: NOR(0,0) = 1  --> B'=1
  Gate 3: NOR(0,1) = 0  --> AND(1,0)=0 -- correct!

Final Answer:
  AND gate requires 3 NOR gates
  OR gate requires 2 NOR gates (NOR then NOT)
  NOT gate requires 1 NOR gate (tie both inputs)

Exam Tip: NOR maps to POS (product of sums) just as NAND maps to SOP. The gate count for NOT, OR, AND using NOR mirrors exactly the NAND counts: NOT=1, OR=2 (one NOR then one NOR inverter), AND=3. GATE often asks for the minimum gate count or gives a circuit diagram and asks which universal gate it uses. Note: OR costs fewer NOR gates (2) than AND costs (3) — this is the exact opposite of NAND where AND costs fewer gates than OR.

Key Properties

• IC 7402: quad 2-input NOR, 14-pin DIP, propagation delay 10 ns at 5 V
• 74HC02: CMOS NOR, 8 ns at 5 V, 2–6 V supply, near-zero static power
• Fan-out: 10 standard TTL loads for 7402
• NOT from NOR: 1 gate (both inputs tied together)
• OR from NOR: 2 gates (one NOR + one NOR used as inverter)
• AND from NOR: 3 gates (two inverters + one NOR) using De Morgan
• NOR preferred in CMOS domino logic: NMOS pull-down stacks are faster than PMOS pull-up

Quick Revision

• NOR is universal: can implement any Boolean function alone
• Y = (A+B)' — output HIGH only when both inputs are LOW
• De Morgan: (A+B)' = A'·B' — NOR = AND with inverted inputs
• NOT = 1 NOR, OR = 2 NOR, AND = 3 NOR
• NOR maps to POS; NAND maps to SOP
• 7402: 10 ns, 5 V, 10 fan-out; 74HC02: 8 ns, 2–6 V, very low power
• OR is cheaper in NOR (2 gates) than AND (3 gates) — opposite of NAND
• Exam trap: thinking OR needs 3 NOR gates — it only needs 2 (NOR output + NOR inverter)