Setup and Hold Time

Every flip-flop in an FPGA routing fabric and every register in a 74HC374 octal latch has a setup time and hold time that the designer must never violate. Missing these constraints causes metastability, the unpredictable behavior that crashes digital systems at random intervals.

Core Concept

Setup time (tsu) is the minimum time the data input D must be stable and valid before the active clock edge for the flip-flop to reliably latch the value. If D changes within the setup window, the flip-flop may enter metastability and its output becomes unpredictable.

Hold time (th) is the minimum time D must remain stable after the active clock edge. The flip-flop's internal latching circuitry needs this window to complete its state change. Violating hold time can corrupt a just-captured value even if setup time was met.

The 74HC74 dual D flip-flop has tsu = 20 ns, th = 3 ns, and tpd(CK→Q) = 25 ns at 5 V. The 74AS74 AS-TTL version has tsu = 4 ns, th = 0 ns, and tpd = 5.5 ns. Modern FPGA flip-flops have tsu and th on the order of tens to hundreds of picoseconds.

Boolean Expression

The timing constraint for a synchronous system is tpd(logic) ≤ Tclk − tsu − tskew. Here tpd(logic) is the combinational path delay, Tclk is the clock period, tsu is the flip-flop setup time, and tskew is the clock skew. The hold time constraint is: tpd(logic) + tpd(FF,CK→Q) ≥ th. Violating either constraint creates a timing error.

Given:
D flip-flop: 74HC74
tsu = 20 ns, th = 3 ns, tpd(CK to Q) = 25 ns
Combinational logic between two flip-flops: tpd = 30 ns
Clock frequency = 20 MHz  → Tclk = 50 ns
Clock skew = 2 ns

Formula / Rule:
Setup check: tpd(logic) + tpd(CK→Q) ≤ Tclk - tsu - tskew
Hold check:  tpd(logic) + tpd(CK→Q) ≥ th + tskew

Step by step (Setup check):
Left side = tpd(CK→Q) + tpd(logic) = 25 + 30 = 55 ns
Right side = Tclk - tsu - tskew = 50 - 20 - 2 = 28 ns
55 ns > 28 ns → SETUP VIOLATION!

Fix: Reduce clock to 10 MHz (Tclk = 100 ns)
Right side = 100 - 20 - 2 = 78 ns
55 ns < 78 ns → Setup met.

Hold check at 10 MHz:
Left side = 55 ns, Right side = 3 + 2 = 5 ns
55 ns > 5 ns → Hold met.

Final Answer:
Minimum Tclk = 55 + 20 + 2 = 77 ns → fmax ≈ 12.9 MHz

Exam Tip: GATE problems on setup and hold time frequently give you all values and ask whether the timing is met. Always write both the setup inequality and the hold inequality and check both. Students often only check setup time. Hold time violations are independent of clock frequency — slowing the clock cannot fix a hold violation. Only adding delay (buffer) in the data path fixes a hold problem.

Key Properties

• 74HC74: tsu = 20 ns, th = 3 ns, tpd(CK→Q) = 25 ns, supply 2–6 V
• 74AS74: tsu = 4 ns, th = 0 ns, tpd(CK→Q) = 5.5 ns, supply 5 V
• Metastability occurs when input changes inside the setup-hold window
• Setup violation: fix by reducing clock frequency or shortening combinational path
• Hold violation: fix by adding buffer delay in the data path — clock slowing does not help
• Clock skew adds to the effective setup time requirement and subtracts from hold margin
• FPGA flip-flops: tsu and th measured in tens to hundreds of picoseconds at modern process nodes

Quick Revision

• Setup time: D must be stable tsu before the active clock edge
• Hold time: D must remain stable th after the active clock edge
• Metastability results from violating either constraint
• Setup constraint: tpd(CK→Q) + tpd(logic) ≤ Tclk − tsu − tskew
• Hold constraint: tpd(CK→Q) + tpd(logic) ≥ th + tskew
• 74HC74: tsu = 20 ns, th = 3 ns, tpd(CK→Q) = 25 ns
• Slowing the clock cannot fix a hold time violation
• Exam trap: checking only setup time and ignoring the hold time inequality