ROM Architecture

ROM holds the BIOS firmware in every PC, the interrupt vector table in every microcontroller, and the character generator patterns in CRT terminals. It is the simplest non-volatile memory architecture, and its internal structure directly shapes how address decoding works in larger memory systems.

Core Concept

A Read-Only Memory (ROM) stores fixed data that persists when power is removed. Internally it has three sections: an address decoder, a memory cell array, and output buffers. The address decoder takes n address lines and activates one of 2ⁿ wordlines. Each wordline connects to a row of m bit cells. The output buffers amplify and gate the selected row's data onto the data bus, controlled by OE (output enable) and CE (chip enable) signals.

The 27C256 is a classic 256 Kbit EPROM organized as 32,768 words of 8 bits (32K×8). It has 15 address lines (A0–A14), 8 data lines (D0–D7), and operates at 5V with access time of 120–250 ns depending on speed grade. The 28C256 is the EEPROM version of the same organization. Mask ROMs (manufactured with data baked in) appear in embedded systems where millions of identical units are made — the data is defined photolithographically.

Capacity is calculated as 2ⁿ × m bits, where n is the number of address pins and m is the data bus width. A ROM with 16 address lines and an 8-bit bus holds 2¹⁶ × 8 = 512 Kbits = 64 KB. In multiple-chip memory systems, higher address bits go to a decoder that generates chip-select signals, while lower bits go to each chip's address inputs — this is called memory banking.

Boolean Expression

ROM implements arbitrary combinational logic. Any Boolean function of n variables with m output bits can be realized in a ROM with 2ⁿ locations of m bits each. The address is the input combination (minterm number), and the stored word is the output. ROM as a logic device: Y = f(A_{n-1}, ..., A_0) where Y is the stored output at address A. This makes ROM a universal combinational logic element — no minimization needed. A truth table IS the ROM contents.

Given:
Implement a 2-bit binary to Gray code converter using ROM
Inputs: B1 B0 (2 bits)  Outputs: G1 G0 (2 bits)
ROM organization: 4 locations × 2 bits (2²×2)

Formula / Rule:
Gray code: G1 = B1,  G0 = B1 XOR B0
Each address (B1B0) stores its Gray code output (G1G0)

Step by step — ROM contents:
Address 00 (B1=0,B0=0): G1=0, G0=0⊕0=0 → store 00
Address 01 (B1=0,B0=1): G1=0, G0=0⊕1=1 → store 01
Address 10 (B1=1,B0=0): G1=1, G0=1⊕0=1 → store 11
Address 11 (B1=1,B0=1): G1=1, G0=1⊕1=0 → store 10

Final Answer:
ROM truth table:
Addr | Data
 00  |  00
 01  |  01
 10  |  11
 11  |  10
Apply address B1B0 → ROM outputs Gray code G1G0

Exam Tip: GATE often asks to calculate ROM size for a given combinational circuit. Always use: number of locations = 2^(number of inputs), word width = number of output bits. Total bits = 2^n × m. A common trap is confusing Kbits with KB — 27C256 is 256 Kbits = 32 KB. Also remember: ROM can implement ANY combinational function of its address inputs without any logic minimization, making it more flexible than a fixed gate network.

Key Properties

• Non-volatile: data retained without power — unlike RAM, no refresh or battery required
• Read-only in normal operation; write (programming) requires special voltage (for PROM/EPROM)
• 27C256: 32K×8, 15 address lines, 8 data lines, tACC = 120–250 ns, VCC = 5V
• Access time for ROM: 45–250 ns — much slower than SRAM (< 10 ns) but faster than HDD
• ROM capacity = 2ⁿ × m bits, where n = address lines, m = data width
• CE and OE pins allow multiple ROM chips to share a data bus via tri-state outputs
• ROM as universal logic: implements any Boolean function of n inputs with m outputs without gates

Quick Revision

• ROM structure: address decoder → memory cell array → output buffers
• n address lines → 2ⁿ wordlines; m data lines → m bits per word
• 27C256 = 32K locations × 8 bits = 256 Kbits = 32 KB
• CE (chip enable) and OE (output enable) control bus access — both active LOW typically
• ROM implements any combinational truth table — no Boolean minimization required
• Mask ROM: data fixed at fabrication — used in high-volume embedded products
• Access time ≈ 120–250 ns for UV EPROM; EEPROM (28C256) ≈ 150 ns read
• Exam trap: confusing ROM capacity in bits vs bytes — always convert: 256 Kbits = 32 KB