PAL

The PAL — Programmable Array Logic — powered most of the glue logic in 1980s PC motherboards and is still the conceptual ancestor of every CPLD and FPGA architecture taught today.

Core Concept

A PAL simplifies the PLA by fixing the OR plane. Each output has a dedicated group of AND-plane product terms hardwired to its OR gate. The user programs only the AND plane, choosing which input literals feed each product term. This makes PAL faster and cheaper to manufacture than PLA, at the cost of losing the ability to share product terms between outputs.

The PAL16L8 from Advanced Micro Devices (AMD) became an industry standard. It offers 16 inputs, 8 combinational outputs, each with 7 product terms, running at 5 V TTL with a 25 ns propagation delay. The 74S330 and MMI PAL16R8 added registered outputs with a D flip-flop on each output, enabling sequential PAL designs.

Modern PAL functionality is embedded inside CPLDs as macrocells. A macrocell typically contains a fixed-width OR gate, an optional flip-flop, and output polarity control. The PAL remains the conceptual building block for understanding CPLDs and the macrocell architecture.

Boolean Expression

A PAL output implements F = P1 + P2 + ... + Pk where k is fixed by the hardware (typically 2-8). Unlike PLA, you cannot borrow product terms from another output's group. If a function needs more product terms than the output's OR gate provides, the design must be split across multiple outputs using an intermediate output feeding back as an input.

Given:
  PAL16L8 with 3 product terms per output
  Implement F(A,B,C,D) = Σm(0,2,8,10,5,7,13,15)

Formula / Rule:
  Each output has exactly 3 product terms in PAL16L8
  Minimize to fit within 3 product terms

Step by step:
  K-map (4 variables):
    Group1: m(0,2,8,10)  → B'D' (2 literals)
    Group2: m(5,7,13,15) → BD (2 literals)
    F = B'D' + BD

  Product term count = 2 ≤ 3 (fits in PAL16L8)
  AND plane: program row 1 = B'·D', row 2 = B·D
  OR plane: fixed, connects row 1 and row 2 to F

Final Answer:
  F = B'D' + BD
  Only 2 of the 3 available product terms used. Third row left unused (fuses all blown → output 0, no effect on OR).

Exam Tip: GATE questions often ask: what happens if a PAL function needs more product terms than the fixed OR gate allows? The answer is product term steering — use an intermediate output (with its own product term group) to implement part of the function, then feed that intermediate output back into the AND plane as an additional literal. This is called 'product term expansion' and is a real PAL design technique. Confusing PAL with PLA (forgetting the fixed OR plane) is the most common error.

Key Properties

• AND plane: programmable (user blows fuses to select literals); OR plane: fixed (hardwired per output)
• PAL16L8: 16 inputs, 8 outputs, 7 product terms per output, 25 ns, 5 V, ~100 mW standby
• PAL16R8: registered variant — 8 D flip-flops on outputs, enabling sequential logic
• No product term sharing between outputs — this is the trade-off versus PLA
• Fan-out: 10 TTL loads for bipolar PAL; CMOS GAL22V10 drives >50 CMOS inputs at 3.3 V
• GAL (Generic Array Logic): EEPROM-based reprogrammable PAL; GAL22V10 is still in production
• Propagation delay: bipolar PAL ~25 ns; CMOS GAL ~5 ns (e.g., GAL16V8B-5 at 5 V, 5 ns)

Quick Revision

• PAL = Programmable AND + Fixed OR, simpler and faster than PLA
• Each output has a fixed, dedicated group of product terms — no sharing across outputs
• Classic IC: PAL16L8 (combinational), PAL16R8 (registered with flip-flops)
• GAL is an EEPROM-based, reprogrammable PAL — same architecture, electrically erasable
• If function exceeds available product terms: use intermediate output and feed back into AND plane
• PAL macrocell concept carries forward into CPLD architecture
• Exam trap: students say 'PAL and PLA are the same' — the critical difference is OR plane: PAL OR is fixed, PLA OR is programmable