FPGA Architecture

When AMD's Xilinx Spartan-7 FPGA runs your video processing algorithm or implements a custom RISC-V core, the same FPGA architecture — a sea of configurable logic blocks, routing fabric, and I/O — makes all of it possible without a single custom transistor.

Core Concept

An FPGA's fundamental compute element is the CLB (Configurable Logic Block). Each CLB in Xilinx 7-series contains two slices; each slice has four 6-input look-up tables (LUTs), eight flip-flops, carry logic, and wide-function multiplexers. A 6-input LUT is a 64-bit SRAM that stores a truth table — the configuration bitstream loads those 64 bits, making the LUT compute any 6-variable Boolean function in one gate delay (~0.1 ns).

The routing fabric connects CLBs through a hierarchy of switch matrices containing SRAM-controlled pass transistors. Long lines span the full chip for clock and high-fanout signals; short local segments connect adjacent CLBs. The Xilinx Spartan-7 XC7S50 has 32,600 LUTs, 65,200 flip-flops, 1800 Kb of block RAM, and 120 DSP48 slices, operating at 1.0 V core with 3.3 V I/O.

Hard IP blocks — Block RAM (18 Kb or 36 Kb true dual-port SRAM), DSP48 slices (18×18 multiplier + 48-bit accumulator), PLLs, and SERDES transceivers — are fixed-function silicon beside the programmable fabric. Using hard blocks for multiply-accumulate is 10-50× more power-efficient than building the same function from LUTs.

Boolean Expression

A 6-input LUT implements F(I5,I4,I3,I2,I1,I0) = SRAM[I5:I0] — the six input bits form a 6-bit address into a 64-entry truth table stored in the LUT's SRAM. Any Boolean function of six or fewer variables maps directly to a single LUT. Two 5-LUT functions that share inputs can be packed into one 6-LUT using the MUXF7 multiplexer, doubling effective LUT utilization.

Given:
  Implement F(A,B,C) = A'B + BC' + A'C' in a 6-input LUT

Formula / Rule:
  LUT stores truth table as 64-bit SRAM word
  Address = {I5,I4,I3,I2,I1,I0} → map A=I2, B=I1, C=I0 (upper inputs tied 0)

Step by step:
  Evaluate F for all A,B,C combinations:
  A=0,B=0,C=0: 0·0+0·1+1·1=1  → bit at address 000 = 1
  A=0,B=0,C=1: 0·0+0·0+1·0=0  → bit at address 001 = 0
  A=0,B=1,C=0: 1·1+1·1+1·1=1  → bit at address 010 = 1
  A=0,B=1,C=1: 1·1+1·0+1·0=1  → bit at address 011 = 1
  A=1,B=0,C=0: 0·0+0·1+0·1=0  → bit at address 100 = 0
  A=1,B=0,C=1: 0·0+0·0+0·0=0  → bit at address 101 = 0
  A=1,B=1,C=0: 0·1+1·1+0·1=1  → bit at address 110 = 1
  A=1,B=1,C=1: 0·1+1·0+0·0=0  → bit at address 111 = 0

  LUT INIT value (hex): addresses 7-0 = 01001101 binary = 0x4D
  Xilinx XDC: INIT="64'h000000000000004D"

Final Answer:
  One 6-input LUT with INIT=0x4D implements F.
  Unused upper address bits I5,I4,I3 are tied to 0.

Exam Tip: GATE asks how many LUTs are needed for a given function. A single k-input LUT implements any function of k variables. For N-variable functions where N > k, synthesis tools decompose them. Remember that FPGA configuration is stored in SRAM, so power-off erases it — an external flash or EEPROM (e.g., Xilinx SPI flash) loads the bitstream at boot. This is why FPGA startup time is non-zero. CPLDs use EEPROM and start instantly.

Key Properties

• CLB = 6-input LUT (64-bit SRAM truth table) + flip-flops + carry chain + MUX logic
• Xilinx 7-series LUT delay: ~0.1 ns intrinsic; routing adds 0.3-2 ns depending on path length
• Block RAM: 18 Kb or 36 Kb true dual-port SRAM per tile; XC7S50 has 100 BRAM tiles = 1800 Kb total
• DSP48E1: 18×18 signed multiplier + 48-bit accumulator + pre-adder, runs at up to 600 MHz
• SRAM-based configuration: volatile, bitstream reloaded from SPI flash at every power-on (~10-100 ms)
• I/O standards: LVDS, LVCMOS, SSTL, HSTL — programmable per pin at 3.3 V, 2.5 V, 1.8 V, 1.2 V
• Xilinx Spartan-7 XC7S50: 32,600 LUTs, 65,200 FFs, 120 DSP48, 1.0 V core, -2 speed grade ~450 MHz

Quick Revision

• FPGA core = grid of CLBs (LUT+FF) + routing switch matrices + hard IP (BRAM, DSP, PLL)
• 6-input LUT = 64-bit truth table SRAM — implements any 6-variable Boolean function
• SRAM-based configuration: volatile — bitstream must reload from external flash after every power cycle
• Block RAM: true dual-port, 18 Kb/36 Kb, used for FIFOs, memories, register files
• DSP48: hard multiplier, far more efficient than LUT-based multiply (area and power)
• Routing hierarchy: local segments (CLB neighbors), long lines (full-chip), global clock trees
• Exam trap: students say 'FPGA configuration is stored in flash on-chip' — wrong. Xilinx 7-series FPGAs use SRAM for configuration; external SPI flash stores the bitstream and loads it at boot