Flash Memory

The SSD in your laptop and the firmware in your microcontroller both live in flash memory — a non-volatile storage technology that holds data without power and can be erased in large blocks at chip speed.

Core Concept

A flash cell is a floating-gate MOSFET with an extra polysilicon gate buried in oxide. Programming (write 0) forces electrons onto the floating gate via Fowler-Nordheim tunneling or hot-carrier injection, raising the threshold voltage. Erasing removes electrons, lowering the threshold back. The control gate voltage then distinguishes a 0 from a 1 by whether the cell conducts.

NOR flash connects cells in parallel between bit line and ground, exactly like a NOR gate. Each cell has its own source-drain connection, enabling random byte-level reads at 70-100 ns. The AMD/Spansion M29W640 is a 64 Mb NOR part running at 3.0 V with a 90 ns access time. It is used for eXecute-In-Place (XIP) firmware in embedded MCUs.

NAND flash connects cells in series, reducing per-cell area dramatically. Reads are page-based (4 KB), not byte-addressed. The Samsung K9F2G08U0C is a 256 MB NAND part with a 25 µs page read time and 2 ms program time. SSD controllers add an FTL (Flash Translation Layer) to map logical addresses, manage wear leveling, and handle bad blocks.

Boolean Expression

A floating-gate cell's threshold voltage shifts: Vth_programmed > Vth_erased. For SLC (Single-Level Cell), logic 1 = erased (low Vth), logic 0 = programmed (high Vth). MLC stores 2 bits per cell with four Vth windows; TLC stores 3 bits with eight windows. More levels per cell means lower endurance and higher bit-error rate, requiring stronger ECC.

Given:
  NAND Flash page size = 4096 bytes
  Block size = 64 pages = 256 KB
  Operation: update 1 byte at address 0x1A3C0

Formula / Rule:
  Flash cannot overwrite; must erase full block before rewriting
  FTL steps: Read-Modify-Write

Step by step:
  1. Identify block containing 0x1A3C0 → Block 6 (addresses 0x18000-0x1FFFF)
  2. Read all 64 pages of Block 6 into RAM buffer
  3. Modify byte at offset within buffer
  4. Erase Block 6 (all 256 KB set to FF hex, ~2 ms)
  5. Program modified data back page by page (64 × ~200 µs = ~12.8 ms)

Final Answer:
  Total time ≈ 14.8 ms for a single byte update.
  FTL uses wear leveling to distribute erases across blocks.

Exam Tip: GATE asks to distinguish NOR from NAND on access method and use case. NOR = random-access, byte-addressable, XIP capable, used for code storage. NAND = page-access only, not XIP, used for data storage. Also remember: you can only program 1→0 (set bits low); to go from 0→1 you must erase the entire block. Erase sets all bits to 1. Write (program) selectively clears bits to 0.

Key Properties

• NOR read latency: 70-100 ns random access; NAND page read: ~25 µs for 4 KB page
• NOR endurance: ~100,000 P/E cycles; SLC NAND ~100,000; MLC ~10,000; TLC ~3,000; QLC ~1,000
• Supply voltage: 1.8 V or 3.3 V for modern NOR/NAND; older devices used 5 V for programming
• Erase granularity: NOR sector ~64 KB; NAND block 256 KB-4 MB depending on geometry
• 3D NAND (V-NAND, BiCS) stacks cells vertically: Samsung V9 = 236 layers, enabling Tb-class chips
• ECC required: NAND raw BER ~10⁻⁸; BCH or LDPC codes correct multi-bit errors per page
• Typical ICs: NOR — M29W640 (64 Mb, 3V); NAND — K9F2G08 (256 MB); eMMC — KLMAG2JENB (128 GB)

Quick Revision

• Flash = floating-gate MOSFET; programming traps electrons on floating gate via FN tunneling
• NOR: parallel cells, byte-random-read, XIP capable, slower write, higher cost per bit
• NAND: series cells, page read, no XIP, fast write throughput, lower cost per bit
• Erase = set all bits to 1 (block level); Program = selectively clear bits to 0 (page level)
• SLC > MLC > TLC > QLC: more bits per cell = lower endurance and higher latency
• FTL handles address mapping, wear leveling, and bad block management in NAND systems
• Exam trap: students write that flash is 'erased to 0' — wrong. Erase sets bits to logic 1 (high Vth removed, cell conducts freely)